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  • #31
    Originally posted by ravyne View Post
    SMT2 is about making use of idle execution units when not enough data-independent instructions can be pulled from the instruction window to saturate the entire CPU core - the reason that these "extra" execution resources exist is either that they are necessary but (relatively) infrequently accessed by a single thread, or because duplicating the execution resources is commonly beneficial to single threads (eg ALUs and AGUs); for the most part, engineers aren't adding execution resources for the benefit of SMT performance gains, specifically.

    SMT4/8 isn't so much about a lack of data-instruction-level parallelism -- though these POWER cores do tend to be wider -- as I understand it, the missed opportunities there tend to be the (relative) lack of data entirely, due to memory latency (hence also the enormous caches to also help compensate)/wild access patterns, or being IO bound. This is why POWER and other SMT-heavy CPUs tend to dominate XEON in applications like databases -- the CPU time needed is peanuts against the time spent waiting on memory fetches that jump all over a huge address space, and then might have to hit disk to top it off -- the CPU itself spends so much time idling that it can soak up 4 or 8 threads.

    The neat thing about POWER, as I understand, is that the CPU isn't always running at SMT4/8, but that it can effectively be running in SMT2 when a core is running 2 heavy threads (it basically never makes sense to disable SMT entirely, unless maybe you had two really hot threads oversubscribing the cache).

    Someone mentioned Knights Landing being SMT4, and that's technically true, but the key detail is that each core has 2 full-blown AVX512 execution units, and the workloads are all heavily AVX512 of course -- the bet there is that 4 threads are what's needed to keep those dual AVX units busy, but the amount of scalar code needed to support the AVX code is relatively little, so one set of scalar execution units is sufficient. It's a bit like a hybrid, Scalar-SMT4/Vector-SMT2 core.
    Its quite funny that IBM for a decade trash talked Sparc Niagara T1 cpus and said T1 had a shitty design, but now, the Power9 copied the T1 design from 2005. Ibm said that T1 8-cores and 4-threads per core, was bad, and the future was Power6 which had two strong cores at 5 ghz because databases run best on few strong cores. Ibm talked about future Power cpus with 1-2 cores clocked at 6-7 ghz, and T1 was dumb. Today ibm has abandoned the few strong core cpus, and instead have many cores and many threads. Just like sparc from 2005. Way to go, ibm. Never mind you need fourteen (14) power6 cpus clocked at 5 ghz, to match four (4) Sparc T2 cpus clocked at 1.6 ghz in official Siebel v8 benchmarks.
    When Sparc does something, it is bad. When ibm copy Sparc a decade later, it is the best thing since sliced bread.

    btw, the Power9 will be 2-2.5x faster than Power8 which means P9 can not catch up on last years Sparc M7, which is 2-11x faster than Power8. The Sparc M7 has 32-cores and 256-threads per cpu. It is the worlds fastest cpu. This year Sparc M8 will arrive, again doubling M7 performance.

    btw, intel xeon is almost 2x faster than Power8 which means Power9 will have a hard time competing with intel xeon and amd epyc

    Comment


    • #32
      Originally posted by Qaridarium

      so you think the "sparc T1" is the best shit ever... and now IBM copy that concept in Power9 so the result should be the best shit ever?...
      so what is your problem with a system like this?... it copied all what you think is nice.. right ?
      I would ignore kebabbert. He sounds like a shill for Oracle.

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      • #33
        Originally posted by Dopefish View Post

        I would ignore kebabbert. He sounds like a shill for Oracle.
        He is. He's been infamous for that in other places (TheRegister, for instance) for ten years or more. Power9 has no real resemblance whatsoever to T1 except for the superficial resemblance that they both have four threads - P9 is a high-clocked deep-OoO core that's far closer to a modern Xeon, microarchitecturally, than to any Sun/Oracle chip.

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        • #34
          Originally posted by Dawn View Post

          He is. He's been infamous for that in other places (TheRegister, for instance) for ten years or more. Power9 has no real resemblance whatsoever to T1 except for the superficial resemblance that they both have four threads - P9 is a high-clocked deep-OoO core that's far closer to a modern Xeon, microarchitecturally, than to any Sun/Oracle chip.
          Maybe I was not clear enough, but I will try to explain again.

          Back in the days, more than a decade ago, IBM trashtalked SPARC T1 and said it was a bad and dumb design, because it used many slower cores instead of 1-2 strong cores. IBM said that databases runs best on 1-2 strong cores, so dual core POWER6 had a better design and was superior to SPARC T1. IBM said the future of cpus was in 1-2 super strong cores clocked at 6-7 GHz or more. Pursuing many weak cores was just stupid. Back in the days, 8-cores SPARC T1 was crazy. The maximum was 1-2 cores, not more.

          So IBM said that the future was 1-2 core cpus with very high GHz. So POWER7,8,9 should be 1-2 cores clocked at 7-8 GHz or so. But they are not. Instead the POWER cpus have.... many lower clocked cores. Just the direction SPARC took more than a decade ago. But back then, that was stupid. Today, when IBM does it a decade later - it is great design. Does not that bother you a bit?

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          • #35
            Originally posted by Qaridarium

            so you think the "sparc T1" is the best shit ever... and now IBM copy that concept in Power9 so the result should be the best shit ever?...
            so what is your problem with a system like this?... it copied all what you think is nice.. right ?
            I dont care that POWER9 did not took the direction that IBM described a decade ago: 1-2 super strong cores and instead went the route of many lower clocked cores just what SPARC T1 was the first to do. IBM can copy the design principle of going many lower clocked cores, instead of 1-2 high clocked cores how much they want. I dont care. What I do care, is that IBM lies and FUDs. Back in the day, they said that having many lower clocked cores was stupid. Today it is not stupid anymore - because IBM does the same. That is what I call FUD.

            In some workloads (SIEBEL v8.0 benchmarks) SPARC T2 cpus at 1.6GHz was more than 10x faster than IBM POWER6 clocked at 5GHz. How can that be stupid? Or was it just FUD?

            "FUD is the fear, uncertainty, and doubt that IBM sales people instill in the minds of potential customers who might be considering Amdahl products" or in this case, SPARC products.

            Comment


            • #36
              Originally posted by kebabbert View Post
              Maybe I was not clear enough, but I will try to explain again.

              Back in the days, more than a decade ago, IBM trashtalked SPARC T1 and said it was a bad and dumb design, because it used many slower cores instead of 1-2 strong cores. IBM said that databases runs best on 1-2 strong cores, so dual core POWER6 had a better design and was superior to SPARC T1. IBM said the future of cpus was in 1-2 super strong cores clocked at 6-7 GHz or more. Pursuing many weak cores was just stupid. Back in the days, 8-cores SPARC T1 was crazy. The maximum was 1-2 cores, not more.

              So IBM said that the future was 1-2 core cpus with very high GHz. So POWER7,8,9 should be 1-2 cores clocked at 7-8 GHz or so. But they are not. Instead the POWER cpus have.... many lower clocked cores. Just the direction SPARC took more than a decade ago. But back then, that was stupid. Today, when IBM does it a decade later - it is great design. Does not that bother you a bit?
              I will use small words, in deference to you.

              No IBM server CPU has ever done "many slower cores." Every generation has faster cores than the predecessor. To reference SPECint, Power5 did 13.5 SPECint_rate2006 per core; Power6 did 33 per core; Power7+ did 55 per core; Power8 did 84 per core. IBM never said "the future of CPUs was in 1-2 super strong cores clocked at 6-7GHz or more" - IBM knew full well by the time Power6 shipped that there were hard limits to frequency scaling (and they were actively exploring aggressive multicore designs with the Cell family.) Power6, like Pentium4, was a clock-oriented "speedracer" design, and the lack of 7GHz chips doesn't prove IBM made a wrong choice somewhere. IBM goes for bigger, meaner cores every generation, consistently. Saying IBM has gone to "many slower cores" is like saying the Core 2 Quad was "many slower cores" vs the 4GHz single-core Pentium4 of the day, when in fact the C2Q was faster in every way - including per-core and on single-threaded code. Clock obsession is something for the mid 90s.

              The fact is, there's a balance point between multithreaded throughput performance and single-thread (and, for licensing reasons, single-core throughput) performance. T1-T3 were way too low on the single-threaded side of that balance for a lot of applications - trust me, I used them, and for loads with any kind of single-threaded sensitivity, they made the old UltraSPARC IV look good. SPARC T4, on the other hand, opted for fewer faster cores than T3, and it was the first Sun/Oracle processor in a long time that was credible (if overpriced) for the kind of workloads my company runs.

              IBM has chosen to go for generally higher single-core and single-thread performance than Oracle but lower multithreaded socket throughput performance (and would you call Kalray, with their chips containing hundreds of simple VLIW cores at a low clock, better than Power or SPARC? Their multithreaded throughput is astounding!). Especially considering their relative pricing, this has caused my company to favor Power over SPARC. That could change, but probably won't unless Oracle decides to change some aspects of their business model.

              I'm not really expecting to convince you on this, seeing as you've been spewing roughly the same copy-pasted claims about the wonders of SPARC and awfulness of IBM for a decade, but I hope this provides food for thought for the others here.

              Comment


              • #37
                kebabbert... as you can clearly see, you are wasting your time here.

                Comment


                • #38
                  Originally posted by kebabbert View Post

                  Its quite funny that IBM for a decade trash talked Sparc Niagara T1 cpus and said T1 had a shitty design, but now, the Power9 copied the T1 design from 2005. Ibm said that T1 8-cores and 4-threads per core, was bad, and the future was Power6 which had two strong cores at 5 ghz because databases run best on few strong cores. Ibm talked about future Power cpus with 1-2 cores clocked at 6-7 ghz, and T1 was dumb. Today ibm has abandoned the few strong core cpus, and instead have many cores and many threads. Just like sparc from 2005. Way to go, ibm. Never mind you need fourteen (14) power6 cpus clocked at 5 ghz, to match four (4) Sparc T2 cpus clocked at 1.6 ghz in official Siebel v8 benchmarks.
                  When Sparc does something, it is bad. When ibm copy Sparc a decade later, it is the best thing since sliced bread.

                  btw, the Power9 will be 2-2.5x faster than Power8 which means P9 can not catch up on last years Sparc M7, which is 2-11x faster than Power8. The Sparc M7 has 32-cores and 256-threads per cpu. It is the worlds fastest cpu. This year Sparc M8 will arrive, again doubling M7 performance.

                  btw, intel xeon is almost 2x faster than Power8 which means Power9 will have a hard time competing with intel xeon and amd epyc
                  Bullshit.
                  Per core, the Power 8 is on par with v3 Xeons.
                  http://www.anandtech.com/show/9567/t...intel-xeon-/10
                  My own personal experience (With Power) more or less validates these results.

                  Can you quote some benchmarks that any credible source did comparing Sparc, Power and Xeon or are you simply inventing stuff as you go along?

                  BTW, I develop code that runs on Xeon, tested on Power and used to work on (far) older Sparc.

                  - Gilboa
                  Last edited by gilboa; 28 July 2017, 06:06 AM.
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                  Comment


                  • #39
                    Originally posted by Dawn View Post

                    I will use small words, in deference to you.

                    No IBM server CPU has ever done "many slower cores." Every generation has faster cores than the predecessor. To reference SPECint, Power5 did 13.5 SPECint_rate2006 per core; Power6 did 33 per core; Power7+ did 55 per core; Power8 did 84 per core. IBM never said "the future of CPUs was in 1-2 super strong cores clocked at 6-7GHz or more" - IBM knew full well by the time Power6 shipped that there were hard limits to frequency scaling (and they were actively exploring aggressive multicore designs with the Cell family.) Power6, like Pentium4, was a clock-oriented "speedracer" design, and the lack of 7GHz chips doesn't prove IBM made a wrong choice somewhere. IBM goes for bigger, meaner cores every generation, consistently. Saying IBM has gone to "many slower cores" is like saying the Core 2 Quad was "many slower cores" vs the 4GHz single-core Pentium4 of the day, when in fact the C2Q was faster in every way - including per-core and on single-threaded code. Clock obsession is something for the mid 90s.

                    The fact is, there's a balance point between multithreaded throughput performance and single-thread (and, for licensing reasons, single-core throughput) performance. T1-T3 were way too low on the single-threaded side of that balance for a lot of applications - trust me, I used them, and for loads with any kind of single-threaded sensitivity, they made the old UltraSPARC IV look good. SPARC T4, on the other hand, opted for fewer faster cores than T3, and it was the first Sun/Oracle processor in a long time that was credible (if overpriced) for the kind of workloads my company runs.

                    IBM has chosen to go for generally higher single-core and single-thread performance than Oracle but lower multithreaded socket throughput performance (and would you call Kalray, with their chips containing hundreds of simple VLIW cores at a low clock, better than Power or SPARC? Their multithreaded throughput is astounding!). Especially considering their relative pricing, this has caused my company to favor Power over SPARC. That could change, but probably won't unless Oracle decides to change some aspects of their business model.

                    I'm not really expecting to convince you on this, seeing as you've been spewing roughly the same copy-pasted claims about the wonders of SPARC and awfulness of IBM for a decade, but I hope this provides food for thought for the others here.
                    Well, it is a fact that IBM said many weaker cores are bad, and that 1-2 fast cores are superior and the future. Today we dont see any IBM POWER cpus with 1-2 strong cores, do we? Can you show us a POWER cpu with 1-2 strong cores?

                    Another example of IBM FUD: It is also a fact that IBM brags about benchmarks and performance all over the internet when IBM has a good cpu (such as POWER7 was the fastest back then) and when IBM loose the performance crown to Oracle later, IBM says that "who cares about performance? Performance is not important and sooo 2000". We see that when IBM's competitors do somethings good, IBM trash talks it. And later when IBM does the same thing, it is the best. That is pure FUD.
                    Oracle CEO Larry Ellison (Wikipedia) Last week, IBM tried to defend its position in the marketplace after Oracle launched its new chips and servers. (Part 1 of a 4-Part Series: How Software on Silicon Will Redefine Enterprise Computing.) In a Wall Street Journal article headlined IBM Fires Back at Oracle After Server [...]


                    "And while it’s not exactly a big surprise that IBM would try to downplay the independent benchmarking tests showing Oracle’s outperformance, IBM’s rationale that businesses don’t care about speed was startling. From the WSJ article:

                    “This was a frozen-in-time discussion,” Parris said in an interview Wednesday. “It was like 2002–not at all in tune with the market today.” Companies today, Parris argued, have different priorities than the raw speed of chips. "

                    But I dont expect to convince you that IBM is the master of FUD. It is a widespread belief in the industry, but not by IBM fanatics.

                    "FUD was first used with its common current technology-related meaning by Gene Amdahl in 1975, after he left IBM to found his own company, Amdahl Corp.: "FUD is the fear, uncertainty, and doubt that IBM sales people instill in the minds of potential customers who might be considering Amdahl products."

                    Comment


                    • #40
                      Originally posted by Qaridarium

                      But Power9 is not "lower cloecked core" it does clock at 4ghz... my 8core FX8320 does have only 3,5 GHZ...

                      even not the modern Ryzen 1700 amd 8core cpu does have 4ghz... a Ryzen 7 - 1700 only do have 3GHZ...

                      so compared to other modern cpus the Power9 clocks very high.

                      so it is not "Lower clocked cores" it is in fact "HIgher Clocked cores."
                      Show us a IBM POWER cpu which has 1-2 very high clocked cores at 6-7GHz or more. IBM said that is the future. Where are those cpus?

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