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Intel Quark SE Support Added To GCC Compiler

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  • Intel Quark SE Support Added To GCC Compiler

    Phoronix: Intel Quark SE Support Added To GCC Compiler

    Support for Intel's low-power Quark SE micro-controller has been added to the GNU Compiler Collection...

    Phoronix, Linux Hardware Reviews, Linux hardware benchmarks, Linux server benchmarks, Linux benchmarking, Desktop Linux, Linux performance, Open Source graphics, Linux How To, Ubuntu benchmarks, Ubuntu hardware, Phoronix Test Suite

  • #2
    WAT? It's not Intel, it's Synopsys ARC.

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    • #3
      Originally posted by Gumix View Post
      WAT? It's not Intel, it's Synopsys ARC.
      Yep, wasn't sure if that was news before or if Synopsys had been snatched up by Intel or what..
      Michael Larabel
      https://www.michaellarabel.com/

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      • #4
        I knew nothing about these CPUs/microcontrollers. Just did some quick reading, it seems the Quark has an ARC core, and an x86 (P54C) instruction decoder. Bizarre. Why? What use is P54C code vs native ARC?

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        • #5
          Originally posted by s_j_newbury View Post
          I knew nothing about these CPUs/microcontrollers. Just did some quick reading, it seems the Quark has an ARC core, and an x86 (P54C) instruction decoder. Bizarre. Why? What use is P54C code vs native ARC?
          I'm very confused as well, especially considering that ARCv2 code density is on par with or better than x86 for the kind of tasks which come to mind when I think of IoT.

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          • #6
            It must be a marketing thing. They can sell the idea it's a "PC" since it's Pentium compatible. I suppose you could run DOS on it!

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            • #7
              Quark SE has an x86 core (486-class, bumped up to P54C ISA level) AND an ARC (EM4) core, which is used as a DSP coprocessor. It's two different cores, not an ARC core with an x86 decoder or something silly like that. I'm not sure how people got the idea that it was.

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              • #8
                Originally posted by Dawn View Post
                Quark SE has an x86 core (486-class, bumped up to P54C ISA level) AND an ARC (EM4) core, which is used as a DSP coprocessor. It's two different cores, not an ARC core with an x86 decoder or something silly like that. I'm not sure how people got the idea that it was.
                That makes even less sense. https://www.synopsys.com/dw/ipdir.php?ds=arc-em4-em6 EM4 is an general purpose CPU for the embedded market, why would you use a general purpose CPU core as a DSP? Furthermore, the P54C ISA has no DSP extensions so any gain from having "compatible" code is lost if you want to utilise the ARC core (for DSP???). I'm sorry, this just doesn't make any sense to me from a technical point of view.

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                • #9
                  Originally posted by s_j_newbury View Post
                  That makes even less sense. https://www.synopsys.com/dw/ipdir.php?ds=arc-em4-em6 EM4 is an general purpose CPU for the embedded market, why would you use a general purpose CPU core as a DSP? Furthermore, the P54C ISA has no DSP extensions so any gain from having "compatible" code is lost if you want to utilise the ARC core (for DSP???). I'm sorry, this just doesn't make any sense to me from a technical point of view.
                  Well plain EM4 is indeed pretty much general purpose MCU/CPU but as all other ARC cores it could be extended by different accelerators which brings us to something more interesting like so-called Sensor Subsystem, see https://www.synopsys.com/dw/ipdir.ph...nsor_subsystem.

                  This additional subsytem requires some specific code to be run on the host (x86 in case of Quark) core but that's how we offload capturing and basic processing of sensor data to low-power co-processor letting a bigger one to rest before all its power is really required.

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                  • #10
                    Originally posted by abrodkin View Post

                    Well plain EM4 is indeed pretty much general purpose MCU/CPU but as all other ARC cores it could be extended by different accelerators which brings us to something more interesting like so-called Sensor Subsystem, see https://www.synopsys.com/dw/ipdir.ph...nsor_subsystem.

                    This additional subsytem requires some specific code to be run on the host (x86 in case of Quark) core but that's how we offload capturing and basic processing of sensor data to low-power co-processor letting a bigger one to rest before all its power is really required.
                    Sounds like you're involved in the development/deployment of the systems in question, so can you comment on the other part of my comment: why a 486/P54C core? Has this come as a side-project from development of the MIC? Intel have used many ISAs and extensions over the years what makes P54C a good choice?

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