EZchip Announces 100 Core 64-bit ARM Chip

[gilboa]

Que the pitchforks, assemble the lynch mob, etc.

FWIW, we're correctly limited to Enterprise DPI.

[gilboa]

What about cache coherency?

Maybe in small clusters (E.g. 4 core groups).

[log0]

What about cache coherency?

Seems to be configurable. Here is an older article talking about it: http://www.theinquirer.net/inquirer/...ases-core-chip

[gilboa]

Seems to be configurable. Here is an older article talking about it: http://www.theinquirer.net/inquirer/...ases-core-chip

Interesting. Thanks.
I would imagine that the performance hit in large clusters (E.g. 16+ cores) will be unusable.
Than again, assuming that the main use case for this CPU is light/mid-end DPI with H/W based load-balancing, inter-core activity should be very low to none.

[marccollin]

another company made a lot of core in a cpu

http://www.azulsystems.com/products/vega/overview

any bench?

[droidhacker]

Que the pitchforks, assemble the lynch mob, etc.

Queue

[cb88]

Queue

Cue




.

[gens]

What about cache coherency?

with a 100 cores ?
probably not

[log0]

Interesting. Thanks.
I would imagine that the performance hit in large clusters (E.g. 16+ cores) will be unusable.
Than again, assuming that the main use case for this CPU is light/mid-end DPI with H/W based load-balancing, inter-core activity should be very low to none.

According to this paper http://www.ecs.umass.edu/mie/tcfd/Papers/InPar12.pdf it seems to scale linearly up to 8 tiles. They also found it to be memory bandwidth limited compared to CPUs and especially GPUs.

After 8 tiles start accessing memory, the
performance with more tiles is relatively small. It has a fast
inter-tile communication network, but we found it very dif-
ficult to use this hardware characteristic to any substantial
advantage for the 4 benchmarks presented here.

[plonoma]

It's for functions such as high throughput firewalls and routers,not Deep Packet Inspection.