Announcement

Collapse
No announcement yet.

EZchip Announces 100 Core 64-bit ARM Chip

Collapse
X
  • Filter
  • Time
  • Show
Clear All
new posts

  • #11
    Originally posted by curaga View Post
    Que the pitchforks, assemble the lynch mob, etc.
    FWIW, we're correctly limited to Enterprise DPI.
    DEV: Intel S2600C0, 2xE52658V2, 32GB, 4x2TB + 2x3TB, GTX1080, F27/x86_64, Dell UP3216Q 4K.
    SRV: Intel S5520SC, 2xX5680, 36GB, 4x2TB, GTX550, F27/x86_64, Dell U2711..
    BACK: Tyan Tempest i5400XT, 2xE5335, 8GB, 3x1.5TB, 9800GTX, F27/x86-64.
    LAP: ASUS Strix GL502V, i7-6700HQ, 32GB, 1TB+256GB, 1070M, F27/x86_64.

    Comment


    • #12
      Originally posted by stalkerg View Post
      What about cache coherency?
      Maybe in small clusters (E.g. 4 core groups).
      DEV: Intel S2600C0, 2xE52658V2, 32GB, 4x2TB + 2x3TB, GTX1080, F27/x86_64, Dell UP3216Q 4K.
      SRV: Intel S5520SC, 2xX5680, 36GB, 4x2TB, GTX550, F27/x86_64, Dell U2711..
      BACK: Tyan Tempest i5400XT, 2xE5335, 8GB, 3x1.5TB, 9800GTX, F27/x86-64.
      LAP: ASUS Strix GL502V, i7-6700HQ, 32GB, 1TB+256GB, 1070M, F27/x86_64.

      Comment


      • #13
        Originally posted by stalkerg View Post
        What about cache coherency?
        Seems to be configurable. Here is an older article talking about it: http://www.theinquirer.net/inquirer/...ases-core-chip

        Comment


        • #14
          Originally posted by log0 View Post
          Seems to be configurable. Here is an older article talking about it: http://www.theinquirer.net/inquirer/...ases-core-chip
          Interesting. Thanks.
          I would imagine that the performance hit in large clusters (E.g. 16+ cores) will be unusable.
          Than again, assuming that the main use case for this CPU is light/mid-end DPI with H/W based load-balancing, inter-core activity should be very low to none.
          DEV: Intel S2600C0, 2xE52658V2, 32GB, 4x2TB + 2x3TB, GTX1080, F27/x86_64, Dell UP3216Q 4K.
          SRV: Intel S5520SC, 2xX5680, 36GB, 4x2TB, GTX550, F27/x86_64, Dell U2711..
          BACK: Tyan Tempest i5400XT, 2xE5335, 8GB, 3x1.5TB, 9800GTX, F27/x86-64.
          LAP: ASUS Strix GL502V, i7-6700HQ, 32GB, 1TB+256GB, 1070M, F27/x86_64.

          Comment


          • #15
            another company made a lot of core in a cpu
            http://www.azulsystems.com/products/vega/overview

            any bench?

            Comment


            • #16
              Originally posted by curaga View Post
              Que the pitchforks, assemble the lynch mob, etc.
              Queue

              Comment


              • #17
                Originally posted by droidhacker View Post
                Queue
                Cue




                .

                Comment


                • #18
                  Originally posted by stalkerg View Post
                  What about cache coherency?
                  with a 100 cores ?
                  probably not

                  Comment


                  • #19
                    Originally posted by gilboa View Post
                    Interesting. Thanks.
                    I would imagine that the performance hit in large clusters (E.g. 16+ cores) will be unusable.
                    Than again, assuming that the main use case for this CPU is light/mid-end DPI with H/W based load-balancing, inter-core activity should be very low to none.
                    According to this paper http://www.ecs.umass.edu/mie/tcfd/Papers/InPar12.pdf it seems to scale linearly up to 8 tiles. They also found it to be memory bandwidth limited compared to CPUs and especially GPUs.
                    After 8 tiles start accessing memory, the
                    performance with more tiles is relatively small. It has a fast
                    inter-tile communication network, but we found it very dif-
                    ficult to use this hardware characteristic to any substantial
                    advantage for the 4 benchmarks presented here.

                    Comment


                    • #20
                      It's for functions such as high throughput firewalls and routers,not Deep Packet Inspection.

                      Comment

                      Working...
                      X