EZchip Announces 100 Core 64-bit ARM Chip

[phoronix]

Phoronix: EZchip Announces 100 Core 64-bit ARM Chip

An Israeli company known as EZchip has introduced their TILE-Mx processors that ship in up to 100-core 64-bit ARM configurations with up to 200 Gigabit Ethernet throughput...

http://www.phoronix.com/scan.php?pag...100-Core-ARMv8

[pipe13]

Following the link, one finds the cores are "ARMv8-A 64-bit ARM Cortex?-A53". These would be the little end of Nvidia's quad-core Tegra K1 ARM, the big end being ARM A57. So this 100-A53-core is targeted at dataserver and network applications, not HPC. But speaking of which, has anyone a clue as to when Nvidia will release a Tegra K1 Denver development kit?

[uid313]

In July 2014, Tilera was acquired by EZchip Semiconductor, a company that develops high-performance multi-core network processors, for $50 million in cash.

This is Tilera technology. It was Tilera who developed the TILE series.

[log0]

So that is what happened to the Tilera, they are replacing the custom vliw cores with A53s.

[toyotabedzrock]

That many arm cores makes me think this is designed for deep packet inspection. Give the nature of the country and available acceleration hardware this might be the real use of this system.

[johnc]

But speaking of which, has anyone a clue as to when Nvidia will release a Tegra K1 Denver development kit?

They won't. K1 is already old news for them.

[liam]

Following the link, one finds the cores are "ARMv8-A 64-bit ARM Cortex?-A53". These would be the little end of Nvidia's quad-core Tegra K1 ARM, the big end being ARM A57. So this 100-A53-core is targeted at dataserver and network applications, not HPC. But speaking of which, has anyone a clue as to when Nvidia will release a Tegra K1 Denver development kit?

I believe K1 used 4 cortex-A15 + 1 cortex-A15.
I think you mean X1, which isn't available yet. IIRC, sometime in the summer is the expected release.

[gilboa]

That many arm cores makes me think this is designed for deep packet inspection. Give the nature of the country and available acceleration hardware this might be the real use of this system.

Most likely the "shallow" side of DPI (E.g. state-full smart routing, etc).
With 100 cores, and 200Gbps, each ARM core has to handle 2Gbps of raw traffic, even if I somehow assume that the H/W load balancer is nearly perfect, doing full packet inspection (E.g. IPS/IDS, network A/V, UTM, forensics, etc) on 2Gbps of traffic requires far more CPU power than a measly A53.

P.S. I'm in the DPI market.

[curaga]

P.S. I'm in the DPI market.

Que the pitchforks, assemble the lynch mob, etc.

[stalkerg]

What about cache coherency?