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  • #11
    Originally posted by duby229 View Post
    Yeah, He and Fred Weber made some pretty awesome products for AMD. Although the architecture Jim Keller is working on pisses me off a little bit. He's dropping CMT in his architecture in favor of SMT. It's probably going to have better power efficiency, but I doubt highly it'll perform well. AMD architectures have always had really high latency on pipeline flushes, and SMT is only going to make it worse. I think it's a terrible decision.
    Yes, but I'm sure the new arch will be designed around SMT. He will fix the latency issues. I have faith. He worked on Apple's CPUs right before this, and they are also great.

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    • #12
      I thought Apple was using Qualcomm processors for their mobile devices, and Intel processors for their PC devices?

      EDIT: Guess not.

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      • #13
        Originally posted by duby229 View Post
        AMD's CMT architecture is organized in what AMD calls "modules". They chose that name because they decoupled the integer pipeline from the floating point pipeline. In doing so it allowed them to add as many integer pipelines as they wanted. In Bulldozer and Vishera there are two integer pipelines and one floating point pipeline. Each integer pipeline has two full function integer units, with two issue ports assigned to them. This configuration is called CMT "Concurrent multi threading". The decoder is shared across all three pipelines. Concerning just the integer pipelines, 89% of the time x86 code will decode into two or less instructions. The other 11% of the time it will decode into more than that. Right now that 11% has no choice but to wait for the next free cycle.

        Going back in time, what made Thunderbird K7 so great was that it had 3 full function integer units, each with it's own dedicated issue port.

        If AMD had done the same thing here, Bulldozer and Vishera would have been much more competitive with Intel's architecture. Which has three full function integer units, plus one part function integer unit and 4 issue ports.

        AMD's architecture can only issue 2 instructions per pipeline, Intel's can issue up to 4. Although 4 isn't very likely, 3 does happen often enough to make a huge difference.
        Is there a place I can read more about this? It's interesting. I understand that Intel is killing AMD ( ) recently in performance and performance per watt, but not an explanation why that I can understand.

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        • #14
          Originally posted by Michael_S View Post
          Is there a place I can read more about this? It's interesting. I understand that Intel is killing AMD ( ) recently in performance and performance per watt, but not an explanation why that I can understand.
          This is a really good article, but it's kinda long winded. It goes into a lot of detail.
          At Hot Chips 2010, AMD released details on their upcoming Bulldozer microarchitecture, intended for server and high-end desktop CPUs. Bulldozer is a high frequency design that is also tailored for multi-core throughput by sharing between cores. Interlagos, the first implementation, will feature 16 cores and debut in mid to late 2011 on a 32nm manufacturing process. This article explores Bulldozer's novel design trade-offs and AMD's new approach to multi-core efficiency.

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          • #15
            Dolk uses his knowledge and insight to bring us an article on how Bulldozer works, and his view on this latest architecture from AMD.


            Here is another simpler article, Though he isn't 100% right. And overclockers.com is known for anti-AMD bias.

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            • #16
              Originally posted by duby229 View Post
              http://www.overclockers.com/bulldoze...ure-explained/

              Here is another simpler article, Though he isn't 100% right. And overclockers.com is known for anti-AMD bias.
              I just wanted to point out for anybody who reads that article, GPU's are not capable of the same precision FP that CPU's are. They are used in very different ways. A GPU will probably never replace a CPU's FP units. A GPU is more similar to a vector processor.
              Last edited by duby229; 26 January 2015, 02:41 PM.

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              • #17
                Thank you for both. I will read them.

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                • #18
                  Thanks for including games in this round of fx testing. Over the weekend I poured over the old reviews of fx processors and there weren't any games included in them. It makes me sure of my very recent (last night) decision of going with an i5 instead of a deeply discounted fx for my new gtx 960 build.

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                  • #19
                    Originally posted by duby229 View Post
                    I just wanted to point out for anybody who reads that article, GPU's are not capable of the same precision FP that CPU's are. They are used in very different ways. A GPU will probably never replace a CPU's FP units. A GPU is more similar to a vector processor.
                    Aren't the SSE FP units IEEE-754 32/64-bit just like modern GPUs ? I thought it was just the older x87 instructions that used 80-bit internally...
                    Test signature

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                    • #20
                      Here are some multi-core benchmarks I did before and after replacing my good ol' Phenom II X6 with an FX-8320E on a very modest motherboard without LLC:

                      OpenBenchmarking.org, Phoronix Test Suite, Linux benchmarking, automated benchmarking, benchmarking results, benchmarking repository, open source benchmarking, benchmarking test profiles


                      You're looking at an overclocked Phenom II X6 (3.9GHz, Corsair A70 air cooling), stock FX-8320E and an overclock to 4.5GHz using Noctua NH-D14.

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