New Intel Diamond Rapids Patch For GCC Confirms AVX10.2-512, APX & Other ISA Features

[phoronix]

Phoronix: New Intel Diamond Rapids Patch For GCC Confirms AVX10.2-512, APX & Other ISA Features

Intel software engineers have been very busy recently with upstreaming various elements of support into the Linux kernel, open-source compilers and more for the next-generation Xeon Diamond Rapids processors. Following the recent GCC prep patches for Diamond Rapids to work on the ISA additions around AMX-AVX512, AMX-FP8, AMX-FP32, and others, a new patch was posted today for actually exposing the "-march=diamondrapids" compiler target and in turn confirming all of the new ISA capabilities...

https://www.phoronix.com/news/Intel-Diamond-Rapids-APX-AVX10

[uid313]

I wonder what APX will mean for x86 and what impact it will have, and if it will make x86 more like ARMv8 and RISC-V.

[Anux]

I wonder what APX will mean for x86 and what impact it will have, and if it will make x86 more like ARMv8 and RISC-V.

It's just more registers that are directly usable (CPUs have much more registers than those you can explicitly use). So you can expect less improvements than we had with the switch to x64. Surely there will be some workloads that profit more but don't expect more than 3 % on average.

[geerge]

A compiler needs to compile APX-aware to make proper use of the extra registers correct? I wonder if software compiled without APX can make use of the extra registers somehow, or if the APX registers are simply turned off to save power.

[AdrianBc]

A compiler needs to compile APX-aware to make proper use of the extra registers correct? I wonder if software compiled without APX can make use of the extra registers somehow, or if the APX registers are simply turned off to save power.

As another poster has also mentioned, all modern high-performance CPUs, including all Intel and all AMD CPUs use the so-callled "register renaming".

That means that the CPUs have a much higher number of registers than specified in the Instruction-Set Architecture, typically between 100 and 200 registers, instead of having only 16 registers.

The instruction decoder, which decodes the instructions into micro-operations, is immediately followed by the register renamer, which allocates some of the unused registers to be used by each micro-operation instead of the registers specified in the instruction code.

The CPU keeps a mapping between the 16 architectural registers and a subset of the real registers, which happens to store the correct values after the retirement of the most recent instructions that had specified those registers.

If a program does not use APX, so its instructions use only 16 registers, all will work like in any previous CPU. If a program uses APX, i.e. 32 architectural registers, it will use the same number of real registers, but a bigger table that maps the 32 architectural registers to the real registers that happen to store their current values.


The performance advantage of APX is not from having more real registers, but in allowing to write without instructions for saving and restoring registers certain programs which require using such register save and restore sequences only because there is no way to encode more registers in the instructions, even if much more registers exist in the hardware. Some of the current x86 programs contain such register save/restore instructions, even if they should not be needed.

[npwx]

So no subscription fees based on the number of bits involved? Wonder what happened to that idea, haven't heard of it in a while.

[Anux]

So no subscription fees based on the number of bits involved? Wonder what happened to that idea, haven't heard of it in a while.

Do you mean Sapphire Rapids on demand or SDSi? That is actually in place. Not sure how successful it is (I hope not at all) because if they fare to well it might come to desktop/laptop too.