Intel & AMD Form An x86 Ecosystem Advisory Group

[dibal]

That clown didn't even know about APX, which basically torpedoes his whole argument. If ISA truly didn't matter, then Intel would have no reason for doing APX.

And ARM would have no reason for doing Neon, AARCH64. etc..

[Anux]

As far as I know, and I think I have verified it in a few places, "RISC" basically means load+store architecture, plus not too many different instruction lengths, plus not many special purpose registers.

As he mentioned, the distinction between RISC and CISC has become smaller over the years and the meaning has altered over time. Back in the 90s the RISC idea was a fixed instruction length ISA with a limited set of instructions that had 1 cycle execution time.
It looks nice from a designer standpoint but limits it's peak performance. It was also a time where CPU circuits were still build by hand (with much less compute assistance atleast), so having a simpler design was valuable.

[coder]

As he mentioned, the distinction between RISC and CISC has become smaller over the years and the meaning has altered over time. Back in the 90s the RISC idea was a fixed instruction length ISA with a limited set of instructions that had 1 cycle execution time.

AFAIK, the original argument of CISC vs. RISC was that simple instructions were easy to pipeline. So, you could either have a CPU with complex instructions that did more work per instructions but they each took multiple cycles, or you could have simpler instructions and execute more of them in the same timeframe. With the pipeline-friendly ISA, it was also easier to take the next step and go superscalar. Before long, RISC won out and most of the CISC folks switched to using microcode that was more like RISC instructions, reaping the attendant benefits.

[dibal]

As he mentioned, the distinction between RISC and CISC has become smaller over the years and the meaning has altered over time. Back in the 90s the RISC idea was a fixed instruction length ISA with a limited set of instructions that had 1 cycle execution time.
It looks nice from a designer standpoint but limits it's peak performance. It was also a time where CPU circuits were still build by hand (with much less compute assistance atleast), so having a simpler design was valuable.

'Load R1 with the Content of the Address 0x0123456789ABCDEF' have the length as 'Add R1 with R2' in the ARM ISA?

[drakonas777]

I see we are blessed with another forum thread where passionate ISA fanboys educated by Apple M1 and Intel Lunar Lake release marketing materials expresses their strong opinion on instructions even though most of them have not written a single assembly line in their life and ISA itself is almost a nil importance in what they do daily with computers in their life

Now, to be more serious, I want to insert equally "important" 2 cents of my own regarding several points made here.

As far as memory channels and BW go, this topic has been mixed with paranoia for years now. Almost every time vendors bump CPU cores someone is dropping that "starved by RAM BW" mantra, because it's the first intuition based reaction. I encourage you to consider 2 facts regarding this topic: a) An average of wide range of real world benchmarks rarely demonstrates CPU to practically limited by RAM. There are outliers of course, but even 2990WX and 3950x on average had a good scaling in the majority of CPU MT practical heavy tasks. b) RAM gets regularly faster. Talking about number of channels alone is meaningless since fast dual channel DDR5 will outperform slow DDR4 quad channel without even getting into things such as CAMM. People always forget this for some reason. That being said I tend to agree we could have one more platform with quad channel and more features in between current mainstream desktop and WS platforms, because the price and feature gap there right now is insane. Furthermore, that hypothetical "affordable HEDT" could exclusively include higher core mainstream SKUs and bleeding edge PCIe rather than adding these to the mainstream platform which makes mainstream mobos expensive and gravitate towards original HEDT price and power consumption. In reality mainstream desktop could be capped at say 8C/16T for AMD and 6P/1T+8E/1T for intel and PCIe 4.0, say <300USD for top i7/R7 SKU, without that i9/R9 segment of course and <100W socket draw. That would be enough for absolute majority of mainstream desktop users because they mostly either play games or use light threaded apps: office suites/CADs/photo editors etc., also mass MT is accelerated by GPUs nowdays. This would make mainstream desktop cost efficient and value oriented, the things it SHOULD BE ABOUT, not a fucking 250W+ behemoth. And of course that "hypothetical HEDT" entry price should be also reasonable that people who need more CPU horsepower for compilation and whatnot could afford it without selling a kidney. That original HEDT "threshold" say 400-600USD entry HEDT CPU and 250-400USD entry HEDT mobo would sound OK for me.

ARM vs x86. I would like to remind you that M3/M4 is NOT what you are getting in Windows/Linux ecosystem and the product properties you get with the average M-based Macbook are not going to be the same to product properties you going to get with average Windows ARM machine, simply because a lot those come not from ARM direcly but rather Apple system design, so at least be practically oriented and compare SDX vs Intel/AMD CPUs since that is going to be the real choice for most of you when buying device for Linux today and in foreseeable future. I agree with "theory" about RISC and ARM advantages over x86, however, the harsh practical reality is I had to go with 6W Intel N100 (which is an old E core now, so image something Skymont based) fanless mini-PC for my home mini-server, because it offered far more value in almost everything (performance, SW compatibility, features even efficiency for my use cases) than any comparable ARM based solution in the same 150-300EUR price range. So when people say x86 is dead it generates a bit of a smile on my face TBH

As for the article itself, the intention behind of all of this is most likely to better organize and minimize differences between Intel and AMD x86 extensions to prevent AVX512-like situation in the future. It's logical and beneficial for everyone.

[kpedersen]

X86 is irrelevant and dying. Panic ensues. It's the Xorg of CPU architectures.

And just like Xorg, nothing feasible has come to replace it yet. The x86* duopoly is going to be a hard one to shake.

Are you going to replace your Intel desktop with an Arm Raspberry Pi? No. Or perhaps you are going to tie yourselves down to a single consumer PC manufacturer (Apple)? No.

Face it; you are currently running an Intel machine (and you are also currently running an X11 server too).

[Anux]

'Load R1 with the Content of the Address 0x0123456789ABCDEF' have the length as 'Add R1 with R2' in the ARM ISA?

Not sure if I understand your question correct. Here's a nice overview straight out of the 90s web: https://www.cs.emory.edu/~cheung/Cou...risc-cisc.html
ARM had 4B instructions and later with Thumb (2B) and Thumb 2 (mixed 2B and 4B). RISC-V has also a variable length instruction set (RVC 2B + 4B) so it should be called CISC-V

[Bounding1662]

Qualcomm and Arm should learn from them instead of being too busy making e-shits that are EOL the next year.

What are you even on about...

[Bounding1662]

Can someone please translate this into English?

I see a ton of buzz words and marketing speak and I can't catch the essence.

Translation: Our bloated, complicated and unmaintainable architecture that spans decades is rapidly becoming irrelevant by ARM and, to an extent, RISC-V microarchitectures and we are scared to death that they will soon break our duopoly and shake up things in computing, and we can't allow that to happen.

[Bounding1662]

Apple M3 beats Lunar Lake on both performance & efficiency, and they're both made on the same TSMC node. M4 is coming soon, and it's on an even better node.


MediaTek is coming. Maybe also Nvidia and AMD, if the rumors are true.

That is plain false, as demonstrated by this.