Intel & AMD Form An x86 Ecosystem Advisory Group

[coder]

In any case the fact is that there is no pure RISC or CISC anymore.

ARM and RISC-V are still pretty much RISC.

[ms178]

What stagnation?
Users can choose between 2, 3 and 4 memory channels, and everyone is buying 2 channels.

Besides, more channels is basically useless. The problem with DRAM is high latency, not low bandwidth. To solve high latency, we have CPUs full of caches.
Bandwidth problem is solved by DDR5 and DDR6, not by adding more memory channels. The bandwidth of DDR5 is already so high that it easily supports GPUs with over 1 Tflops of compute power.
The same high bandwidth of DDR5 is available to CPU cores, and they don't really benefit much from increased DRAM bandwidth. Additional memory channels would add more bandwidth, and since bandwidth is already excessive, there is no need for more memory channels.

Just give me a X58-like experience again. With cheap overclockable used server CPUs after a couple of years while at it. Threadripper is not prosumer territory any longer as it comes with a workstation price tag. I want to see more innovation in memory technology in the affordable consumer space.

By the way, we need both, high bandwith and low latency. AMD can't even feed the AVX-512 vector engines according to the Y-cruncher dev, showing that bandwith also matters in some workloads. And as we peasents won't get HBM, I gladly take any other innovation which yield substantial performance benefits. It is laughable that you can get 450+ USD motherboards nowadays that don't even properly support ECC memory and come with only two memory channels.

[edxposed]

What stagnation?
Users can choose between 2, 3 and 4 memory channels, and everyone is buying 2 channels.

Besides, more channels is basically useless. The problem with DRAM is high latency, not low bandwidth. To solve high latency, we have CPUs full of caches.
Bandwidth problem is solved by DDR5 and DDR6, not by adding more memory channels. The bandwidth of DDR5 is already so high that it easily supports GPUs with over 1 Tflops of compute power.
The same high bandwidth of DDR5 is available to CPU cores, and they don't really benefit much from increased DRAM bandwidth. Additional memory channels would add more bandwidth, and since bandwidth is already excessive, there is no need for more memory channels.

In fact, the single-threaded read bandwidth of 9950X is around 55GB/s, while the actual multi-threaded read bandwidth with the default 128-bit DDR5-5600 is 60GB/s. I don't think that's "enough".

[isaacx123]

Apple M3 beats Lunar Lake on both performance & efficiency, and they're both made on the same TSMC node. M4 is coming soon, and it's on an even better node.


MediaTek is coming. Maybe also Nvidia and AMD, if the rumors are true.

Apple M3 beats Lunar Lake on ASIC benchmarks, on real benchmarks like software compilation (eg Chromium compile time) or software video encoding (eg x265) Lunar Lake destroys the M3.

[coder]

AMD can't even feed the AVX-512 vector engines according to the Y-cruncher dev,

Y-cruncher isn't representative of most AVX-512 apps. Michael just tested a 128-core Zen 5 CPU with different DDR5 speeds and most AVX-512 heavy workloads didn't benefit nearly as much as the DRAM speed difference would suggest.

https://www.phoronix.com/review/amd-epyc-9755-ddr5

BTW, it was the same actual DRAM, so the latency (in terms of nanoseconds) was the same for both runs.

as we peasents won't get HBM, I gladly take any other innovation which yield substantial performance benefits.

Okay, so get a Strix Halo, when it launches.

It is laughable that you can get 450+ USD motherboards nowadays that don't even properly support ECC memory and come with only two memory channels.

What's funny about that?

In fact, the single-threaded read bandwidth of 9950X is around 55GB/s, while the actual multi-threaded read bandwidth with the default 128-bit DDR5-5600 is 60GB/s. I don't think that's "enough".

What's "enough" is defined by the DRAM speed at which your app no longer gets faster, not whatever you arbitrarily decide.

The fact is that most apps have a pretty high cache hit rate, or else CPUs wouldn't have so much of it.

[illwieckz]

My first proposal to AMD and Intel - make more than 2 memory channels for consumer CPUs. That was enough when they had 4 cores and next 4+ cores processor was 1000$ (thanks Intel). Now when we have 16/32 in desktops having pathetic 2 64bit 4 32-bit channels DDR5 memory kills all the performance from those cores.

Some years ago at the time the memory was still DDR4 and AMD was still selling Zen 2 I got a 16/32 ThreadRipper PRO with 8 channels of memory. The only reason why the CPU and the motherboard was marketed a bit higher than the 16/32 Ryzen counter part (and I even got it for the same price because I stumbled on a very good offer) was because that also features 7 complete PCIe 4 x16 and 8 DIMM slot, so you have to pay for the extra features, not just for the octachannel thing. The public price difference between the Ryzen and the TR PRO was just for the extra features, not some artificially inflated “PRO” price we can see in GPU market for example. In the end the whole computer was even cheaper because the ECC server RAM was actually cheaper than non-ECC consumer RAM at the time.

I guess similar moves can be done with current ThreadRipper PRO and DDR5 RAM today. I guess you can totally get octachannel DDR5 with Zen 4 ThreadRipper PRO if you're ready to pray the extra price of buying 8 DIMMs of RAM and pay for the 7 full PCIe 5. The extra price compared to Ryzen with same core count is likely the one for the extra features that should be paid anyway. If you can't pay for the extra feature, then it's not the vendor's fault.

[coder]

Apple M3 beats Lunar Lake on ASIC benchmarks,

Also on things like Geekbench 6 ST & MT. In Cinebench R24, MT is a tie but the M3 clobbers it on ST. CrossMark.

https://www.notebookcheck.net/Intel-Lunar-Lake-CPU-analysis-The-Core-Ultra-7-258V-s-multi-core-performance-is-disappointing-but-its-everyday-efficiency-is-good.893405.0.html

Efficiency-wise, the M3 eats Lunar Lake for breakfast.

on real benchmarks like software compilation (eg Chromium compile time) or software video encoding (eg x265) Lunar Lake destroys the M3.

Bullshit. Show me these benchmarks. It's probably doing something stupid, like comparing each CPU on compilation for its own ISA - not true apples-to-apples.

[Espionage724]

And now I'll start considering RISC-V and ARM viable alternatives

I'm not tied to X86; I ran World of Warcraft (SL/retail) ARM64 on a OnePlus 6 and regardless of the amount of duct-tape needed to get Windows ARM onto it natively, WoW just-worked at great performance.

And the idea of sketchy Intel and less-publicly-sketchy AMD coming together to form a group to define X86 throws up a lot of red flags to me. Feels like these "collaboration and innovations" are going to be financially-driven with back-room discussions; nothing at all open or inviting to be open. Heck a cheap RPi with ARM feels more inviting to me to mess with; I just happen to have more-powerful X86 hardware lying around

[coder]

Dvorak keyboards have lost (not because they are inferior).

I'm using one. And yes, it actually implements the mapping in hardware and has dual keycaps.

[ms178]

What's funny about that?

Maybe there was a misunderstanding with the way I phrased it, I find it sad to see a big price tag with very little substantive gains in functionality for that price. But appearently marketing and some OC features sell these high priced boards. People still won't get any more PCIe lanes or anything what I would call substantive.

Okay, so get a Strix Halo, when it launches.

Indeed, I already planned to closely watch how Strix Halo performs. Apple's M1+ and Lunar Lake proved in principle that this concept can yield some impressive efficiency gains. I hope this will also stay true at a higher performance tier.