Intel & AMD Form An x86 Ecosystem Advisory Group

[IsolatedOctopi]

you are just asking about having server architectures as home PCs,

thanks to us that's coming, we already have 4 channels of memory if using DDR5

is more about PCIe specifications, than about Intel CPUs

personal computers always had less compute power, that's why you cannot expect have data center perfomance at home

yet you can always get a NVidia DGX Workstation and sleep happy while you read news on a 49,900$ personal workstation

more about Intel Xeon

1. • Each Intel Xeon Scalable processor has two memory controllers. This is a key difference from consumer CPUs, which typically have only one memory controller.
   • Each memory controller supports three memory channels. Therefore, each Xeon processor has a total of six memory channels.
   • In a dual CPU system (using two Intel Xeon processors), you would have twelve memory channels in total.
2. Memory Channel and DIMM Configuration:
   • Unlike DDR5 consumer memory sticks that support only two channels per stick, Intel Xeon Scalable processors can utilize more channels due to their advanced memory architecture.
   • Each channel supports up to two DIMMs, resulting in a maximum of twelve DIMMs per processor (six channels × two DIMMs) for full performance.

[loganj]

all i could read is "blah blah blah"

[ms178]

Not very inventive.
I.e. AMD Threadripper already has 4 memory channels. People didn't flock to buy Threadrippers.
Threadripper is a consumer CPU (i.e. for "enthusiast" segment, but also for some small businesses).

Considering that we already had three memory channels with X58, it is a bit sad to see the stagnation on that front. I get it that it is about motherboard real estate and added complexity and costs, but considering the current motherboard pricing, it should be an option for mid- to high tier models. Maybe something like MCDIMMs or CXL-modules are the future though.

[isaacx123]

Great, I hope something good comes out of it, maybe standardization of the complete AVX-512 instruction set for consumer CPUs.

I don't know why a lot of people on here and the open source community as a whole have such animosity towards x86, and some even wish the death of it, while ARM is still a joke in both raw power and now efficiency as demonstrated by Lunar Lake.

Also the only two worthwhile ARM SoC (Apple and Qualcomm) manufactures are extremely hostile (Qualcomm to a lesser degree) towards open source operating systems, as demonstrated by Qualcomm poor driver support for the Snapdragon X on Linux.

[rmfx]

They look like 2 boomers who can't stand each other teaming up against newly installed young adults, to keep the neighbourhood bylaws to their advantage.

[V1tol]

Not very inventive.
I.e. AMD Threadripper already has 4 memory channels. People didn't flock to buy Threadrippers.
Threadripper is a consumer CPU (i.e. for "enthusiast" segment, but also for some small businesses).

Buy Threadripper, cheapest of which costs 1299$ (12/24 7945WX, 4 channels) instead of consumer 9950X for 623$. Probably nice being you. I am asking not for a Threadripper for crap tons of money, I am asking for consumer Ryzens with at least 3 channels. Let it be only for 2 CCD-based CPUs only.

[coder]

I don't know why a lot of people on here and the open source community as a whole have such animosity towards x86, and some even wish the death of it, while ARM is still a joke in both raw power and now efficiency as demonstrated by Lunar Lake.

Apple M3 beats Lunar Lake on both performance & efficiency, and they're both made on the same TSMC node. M4 is coming soon, and it's on an even better node.

Also the only two worthwhile ARM SoC (Apple and Qualcomm) manufactures are extremely hostile (Qualcomm to a lesser degree) towards open source operating systems, as demonstrated by Qualcomm poor driver support for the Snapdragon X on Linux.

MediaTek is coming. Maybe also Nvidia and AMD, if the rumors are true.

[muncrief]

This is great. Despite cries of impending doom x86 is a great ISA that regularly outperforms semi-RISC type processors like ARM and others.

In any case the fact is that there is no pure RISC or CISC anymore. In fact both architectures are moving closer to each other, with semi-RISC processors driving x86 designs to use less power, and CISC processors driving semi-RISC to deliver more performance.

Heck, I remember working on my first RISC processor at Olivetti Advanced Technology center in 1992, where I designed the high speed multiplier/divider and VGA format processor module, and assisted in the design of the pipelined RISC processor, ISA host bus interface, and memory management modules - and being shocked at the incredible inefficiency of pure RISC.

I mean good lord, there were something like 16 registers total, and instead of a single push and pop instruction each one had to be individually addressed. This required 16 individual instructions with all the commensurate reading, decoding, and memory access cycles, which was just a monumental waste of time.

Yet when I suggested adding microcode to execute push/pop and other instructions more efficiently I was considered a heretic because it violated the "RISC philosophy", which was all about using as few transistors as necessary to implement fixed length instructions, and performance be damned.

While on the CISC side too many instructions that could have been handled in a more RISC type way were continually added, which resulted in the extremely complex CISC instruction decode cycles that adversely affect its performance.

So the answer isn't either/or, it's both. Like that old saying - "Use the right tool for the right job" - don't get caught up in the dogma, simply do what works best.

[ssokolow]

Perhaps because x86 looks like a pretty shitty ISA, at least on a first glance.
In theory, other ISA should allow for somewhat greater speed and higher efficiency. Of course, that has yet to be proven, although other ISA are already a match to x86 in speed, and they are better in efficiency.

Dvorak keyboards.

[coder]

My first proposal to AMD and Intel - make more than 2 memory channels for consumer CPUs.

CUDIMMs are here and will help scale bandwidth further.

In Q1 of next year, AMD will launch Strix Halo (for laptops), that has a 256-bit on-package memory interface (similar to Apple's M2 Pro). Eventually, on-package memory will probably come to desktops. That's a more power-efficient way to scale bandwidth than by adding more DIMM slots to your motherboard.