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RISC-V Wires Up More Kernel Features With Linux 6.12

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  • RISC-V Wires Up More Kernel Features With Linux 6.12

    Phoronix: RISC-V Wires Up More Kernel Features With Linux 6.12

    The RISC-V architecture updates have been submitted for the Linux 6.12 kernel cycle. More RISC-V CPU ISA extensions are being supported along with enabling some additional kernel features for this CPU architecture...

    Phoronix, Linux Hardware Reviews, Linux hardware benchmarks, Linux server benchmarks, Linux benchmarking, Desktop Linux, Linux performance, Open Source graphics, Linux How To, Ubuntu benchmarks, Ubuntu hardware, Phoronix Test Suite

  • #2
    Nice updates for RISC-V, Explaininf Computers channel showed that RISC-V is starting to become stable and maybe pratical, with the Banana Pi BPI F3,i predict we will have RISC-V computers that are pratical for Linux nerds in 2025.

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    • #3
      On the embedded world the ESP32, latest is the esp32p4 a dual-core 400mhz and single core low power 40mhz, is already on the RISC-V wagon.
      Raspberry foundation joined recently with the pico2 which has dual-core / dual-architecture and it's possible to run 1 ARM + 1 RISC-V core together.

      In a recent interview Linus said that RISC-V is repeating the mistakes of its predecessors, but it's not clear to me what he meant to say.
      Last edited by ari55; 27 September 2024, 01:17 AM.

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      • #4
        I am all for RISC-V so don't get me wrong, but it is a bit funny when the main idea of the ISA was to make it so that code can be run anywhere, and almost every time I see some RISC-V news it mentions extensions...

        http://www.dirtcellar.net

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        • #5
          Originally posted by waxhead View Post
          I am all for RISC-V so don't get me wrong, but it is a bit funny when the main idea of the ISA was to make it so that code can be run anywhere, and almost every time I see some RISC-V news it mentions extensions...
          RISC-V is meant to be a modular ISA, suitable for lots of tasks, so the ideia is that the base ISA is small to fit in tiny microcontrollers, and you can add extensions for larger CPUs. (There is even a RISC-V GPU project, wich is just a regular CPU with a huge vector unit and special instructions for textures and pixels)

          It may cause fragmentation, but RISC-V has solved that with standard Application profiles, wich are named RVAxx. (Where xx is the year, like RVA22 for 2022)

          These profiles are meant to be the bare minimum set of extensions supported by software, currently most distros require at least GC extensions. (G being a set of general purpose extensions, C for compressed instructions)

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