Linux Prepares For Intel Arrow Lake H With Mix Of Lion Cove, Skymont & Crestmont Cores

[phoronix]

Phoronix: Linux Prepares For Intel Arrow Lake H With Mix Of Lion Cove, Skymont & Crestmont Cores

With upcoming Intel Arrow Lake H processors it's just not P cores and E cores but for the E cores will be a mix of both Skymonth and Crestmont core types...

https://www.phoronix.com/news/Intel-ARL-H-3-Core-Types

[tildearrow]

Typo:

Skymonth

My.... I remember in 2013 when they planned Skymont as the successor of Skylake. Eight years later, we finally see it.

[bezirg]

I cannot believe this. 3 different micro-architectures? Performance cores, efficiency cores and then what? Efficiency-but-bad-performance cores?

[numacross]

I cannot believe this. 3 different micro-architectures? Performance cores, efficiency cores and then what? Efficiency-but-bad-performance cores?

LPE-cores - Low Power Efficiency cores.
Meteor Lake has them too, but using the same microarchitecture as its E-cores. They also live outside of the main core chiplet, and are not on the Ring Bus which drastically increases core-to-core latencies for them. The idea was for the main core chiplet to be completely powered down while the LPE-cores could handle periods of inactivity.

(source)

[milkylainen]

I remember someone famous calling Intel out for not being able to stick to simple, instead of over-complicated things.
More scheduling horror stories? I dunno.

[aerospace]

I hope kernel guys send Intel the bill for the programming and testing needed...2 different E-cores and 2 GPU archs combinations in 5 SKU..what could possibly go wrong?

[AdrianBc]

I cannot believe this. 3 different micro-architectures? Performance cores, efficiency cores and then what? Efficiency-but-bad-performance cores?

Actually it was well known that Arrow Lake H will include Crestmont cores.

Arrow Lake H is only an upgrade for the existing Meteor Lake. It will replace the CPU tile, but it will keep the same I/O tile.

The GPU tile of Arrow Lake H is likely to be only a refresh of that of Meteor Lake, perhaps with a slightly higher clock frequency, because it is known that it will not have the new Xe2 architecture that is used in Lunar Lake.

Despite the fact that Lunar Lake will be launched first, the design of Arrow Lake H has started a long time before Lunar Lake, so its CPU does not have some instructions available in Lunar Lake and its GPU uses the old architecture. The reason why Lunar Lake has leapfrogged Arrow Lake H is because Intel has given up to use for Lunar Lake their own manufacturing, as initially announced, but they have retargeted the design of Lunar Lake for a TSMC CMOS process, which has allowed them to complete the Lunar Lake design sooner, without having to wait for their own CMOS process to become usable.

While the new CPU tile of Arrow Lake H will have up to 6 Lion Cove cores and up to 8 Skymont cores, the I/O tile that is inherited from Meteor Lake contains 2 lower-power Crestmont cores, to be used when the CPU tile is powered down, e.g. for watching a movie. This is why there are 3 kinds of cores. Meteor Lake also has 3 kinds of cores, but 2 kinds happen to use the same Crestmont structure, albeit at different clock frequencies.

[cl333r]

I cannot believe this. 3 different micro-architectures? Performance cores, efficiency cores and then what? Efficiency-but-bad-performance cores?

I guess ARM based solutions don't have to do this because they're efficient from the ground up?

[duby229]

I don't get it. I thought cores on a platform all had to support exactly identical ISAs? What happens when a process gets scheduled to a core that doesn't support an instruction it was compiled with? Is there gonna need to be a runtime compiler to recompile on the fly? Or do you just compile to the least common denominator? What about optimizations for the more capable cores?

I really don't get it ..

[AdrianBc]

I guess ARM based solutions don't have to do this because they're efficient from the ground up?

Almost all smartphone CPUs of the last 4 years use 3 kinds of cores, at least one Cortex-X* core, optimized for single-thread performance (corresponding to the Intel P-cores), some Cortex-A7* cores, optimized for multi-threaded performance (corresponding to the Intel E-cores) and a few low-power Cortex-A5* cores, to be used for background tasks (corresponding to the Meteor Lake and Arrow Lake H Crestmont cores of the I/O tile).


Even the low cost smartphone CPUs use 3 kinds of cores, where the more expensive Cortex-X* core is replaced by a Cortex-A7* core that has a higher clock frequency and a bigger cache memory than the other Cortex-A7* cores.