SMT Performance Benchmarks Continue To Show Benefit With AMD Zen 5/5C

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  • qarium
    Senior Member
    • Nov 2008
    • 3438

    #91
    Originally posted by coder View Post
    Theoretically, you can spawn threads sharing the same code & data, with one not impacting the L2 cache available to the other. In practice, this level of sharing is probably quite rare and you're right that multiple SMT threads would reduce cache & memory bandwidth available to the other.
    "In practice, this level of sharing is probably quite rare"

    exactly... these people who defend SMT/hyperthreating they claim the exactly opposite of what you say.
    Phantom circuit Sequence Reducer Dyslexia

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    • mahirzukic
      Junior Member
      • Mar 2024
      • 7

      #92
      Once again I call upon @phoronix and Michael Michael to give us some actual numbers. For example amount of RAM used with HT in relation to without HT averaged over 300 something tests he has. I think he could do it with this very processor as well, so that we can compare the RAM increases with the performance increase (18%).

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      • qarium
        Senior Member
        • Nov 2008
        • 3438

        #93
        Originally posted by mahirzukic View Post
        Once again I call upon @phoronix and Michael Michael to give us some actual numbers. For example amount of RAM used with HT in relation to without HT averaged over 300 something tests he has. I think he could do it with this very processor as well, so that we can compare the RAM increases with the performance increase (18%).
        exactly this is what we need.

        A number like 18% performance increase for a 5000€ cpu if you have to spend 7000€ more in ram is not as good as people may thing.

        in the past people had no choice intel had monopole and there was no high performance option without hyperthreating...

        also keep in mind for gamers its not only ram its also input latency and if you disable hyperthreating you get 5-6% better latency....

        people buy nvidia cards for nvidia reflex for better latency so why waste the latency on hyperthreating ?
        Phantom circuit Sequence Reducer Dyslexia

        Comment

        • Ladis
          Senior Member
          • Feb 2017
          • 408

          #94
          Originally posted by mahirzukic View Post

          7zip is just one such program which falls into the first category of 0% data sharing.
          You are cherry picking buddy.
          I already told you overwhelming majority of programs fall into the 3rd category where there is some data during between threads.
          ​Most of the algorithms have own set of data for each thread. Because sharing data is a slowdown, as the communication between the cores has to increase (and sux for Intel's small cores and AMD between chiplets). Also Apple shares a lot of data through the unified memory model (shared L2 cache mong CPU and coprocessor cores).

          Originally posted by zeealpal View Post

          Also, from a uArch perspective which has already been mentioned but not compared here is the transistor budget to achieve the results.
          • Apple M3-Pro: 37b transistors.
          • Apple M4: 28b transistors.
          • Ryzen 9 7945HX3d: 17.8b transistors.
          Obviously there are trade-offs for power vs area, general vs accelerator etc... but it's easy to say a processor is more performant / power efficient, but when it costs 50% more to make it's less of an achievement.

          ​But it doesn't cost 50% more for Apple, as he pays no middle man and orders directly from TSMC. That was the point.

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