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Shopping For A Launch-Day AMD Ryzen AI 300 Series Laptop For Linux Testing

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  • #11
    Originally posted by sophisticles View Post
    That ASUS Zenbook S is so much nicer than anything Framework, System76, and TUXEDO put out and at a much better price point.

    It makes sense, Asus is a bug player and can afford to sell their products at a more competitive price point, those other three are probably barely treading water and don't have the same flexibility.
    Hmmm... there might be a typooboo lurking somewhere therein. But how would one tell?

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    • #12
      To be fair, given the screen size and resolution, RAM, CPU and storage size, the price seems quite reasonable for a VFM laptop that should last for a few years (regardless of the AI capabilities, which I hope can be somehow disabled, just in case).

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      • #13
        ASUS Ryzen AI 9 HX 370 laptops with integrated graphics:All models come with soldered RAM, 24-32GB.
        Last edited by avis; 06 June 2024, 03:33 PM.

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        • #14
          There's still only 1 laptop that sports a 7900M and it appears to be sold only in America

          Come on AMD take my money already!

          Let's hope theres an international option for a highend RDNA4 when it's released

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          • #15
            Can the AI NPU be used for non AI tasks? OpenCL? ROCm? OpenCV? Pytorch? Ffmpeg? Vulkan compute? Tensorflow? FPGA-like digital circuit emulation? Real-time image processing? Real-time audio processing? Network processing?

            I know these AI cores are based on Xilinx Versal heterogeneous stuff, but not sure how much. Do they contain all parts? All except CPU cores? Maybe all except the ARM cores No idea.

            Any plans for these evolved Xilinx Versal cores be supported by ROCm? Or are they their own stuff and only able to use petalinux? Can someone explain this in an abierto but detailed way outside the insane AMD docupropaganda?

            Last edited by timofonic; 06 June 2024, 07:22 PM.

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            • #16
              Originally posted by timofonic View Post
              Can the AI NPU be used for non AI tasks? OpenCL? ROCm? OpenCV? Pytorch? Ffmpeg? Vulkan compute? Tensorflow? FPGA-like digital circuit emulation? Real-time image processing? Real-time audio processing? Network processing?

              I know these AI cores are based on Xilinx Versal heterogeneous stuff, but not sure how much. Do they contain all parts? All except CPU cores? Maybe all except the ARM cores No idea.

              Any plans for these evolved Xilinx Versal cores be supported by ROCm? Or are they their own stuff and only able to use petalinux? Can someone explain this in an abierto but detailed way outside the insane AMD docupropaganda?

              https://ir.amd.com/news-events/press...ership-in-data
              It's funny to think you can ask the laptop this question about its own capabilities, given it has the right software.

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              • #17
                Nice, I was looking at this very same laptop. I want to go with either this Ryzen chip or the Snapdragon X Elite. Looking forward to the results.

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                • #18
                  Originally posted by krzyzowiec View Post
                  Nice, I was looking at this very same laptop. I want to go with either this Ryzen chip or the Snapdragon X Elite. Looking forward to the results.
                  I pre-ordered it today with not finding any other pre-order options since that fit my criteria, so around 16~17 July expect (early) results if indeed it arrives for 15 July as stated.
                  Michael Larabel
                  https://www.michaellarabel.com/

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                  • #19
                    Originally posted by krzyzowiec View Post
                    Nice, I was looking at this very same laptop. I want to go with either this Ryzen chip or the Snapdragon X Elite. Looking forward to the results.
                    By the way, are or will be all Snapdragon drivers mainline, especially GPU? Is this a criteria for you?

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                    • #20
                      Originally posted by Mitch View Post

                      It's funny to think you can ask the laptop this question about its own capabilities, given it has the right software.
                      I doubt it. I experimented with a LLMs and only managed the following after tons of iterations and guiding. And ask to generate very specific stuff separately. Etc. And the result is mediocre. I had to do some modifications.

                      Ryzen AI processors combine traditional x86-64 CPU cores, GPU and NPU.

                      Code:
                      ┌─────────────────────────────────────────────────────────────────────────────┐
                      │                                Ryzen AI                                     │
                      │ ┌─────────────┐   ┌────────┐   ┌────────┐   ┌─────────────┐   ┌──────────┐ │
                      │ │ x86-64 Cores│──►│ GPU    │──►│ XDNA2  │──►│ PC Peripherals│ │          │ │
                      │ └─────────────┘   └────────┘   └────────┘   └─────────────┘   └──────────┘ │
                      └─────────────────────────────────────────────────────────────────────────────┘

                      Code:
                      ┌─────────────────────────────────────────────────────────────────────────────┐
                      │                                   NPU                                       │
                      │ ┌─────────────┐   ┌─────────────┐   ┌─────────────┐   ┌─────────────┐      │
                      │ │ AI Engines  │──►│ DSP Blocks  │──►│ Memory Ctrl │──►│ I/O Ports    │      │
                      │ └─────────────┘   └─────────────┘   └─────────────┘   └─────────────┘      │
                      │                                                                             │
                      │ ┌─────────────┐   ┌─────────────┐   ┌─────────────┐   ┌─────────────┐      │
                      │ │ Codecs      │──►│ Cache       │──►│ Data Fabric │──►│ Power Mgmt   │      │
                      │ └─────────────┘   └─────────────┘   └─────────────┘   └─────────────┘      │
                      └─────────────────────────────────────────────────────────────────────────────┘
                      - **AI Engines**: Specialized cores designed for AI computations.
                      - **DSP Blocks**: Digital Signal Processing units for handling complex mathematical functions.
                      - **Memory Control**: Manages the flow of data in and out of the NPU's memory.
                      - **I/O Ports**: Input/Output interfaces for external communication.
                      - **Codecs**: Used for encoding and decoding digital data streams.
                      - **Cache**: Temporary storage for quick data access.
                      - **Data Fabric**: The network within the NPU that connects different components.
                      - **Power Management**: Regulates power usage within the NPU to ensure efficiency.

                      Code:
                      ┌─────────────────────────────────────────────────────────────────────────────┐
                      │                              AI Engine Tile                                │
                      │ ┌──────────────────────┐   ┌─────────────────────┐   ┌───────────────────┐ │
                      │ │ Tile Interconnect    │──►│ Memory Module       │──►│ AI Engine          │ │
                      │ │ Module               │   │                     │   │                     │ │
                      │ └──────────────────────┘   └─────────────────────┘   └───────────────────┘ │
                      │       │                         │                         │                │
                      │       │                         │                         │                │
                      │       │  ┌──────────────────────┴──────────────────────┐  │                │
                      │       │  │ 32 KB Data Memory divided into 8 banks      │  │                │
                      │       │  │ Memory Interface, DMA, Locks                │  │                │
                      │       └─►│ Access to neighboring tile memories         │  │                │
                      │          └──────────────────────┬──────────────────────┘  │                │
                      │                                 │                           │                │
                      │                                 │  ┌──────────────────────┐ │                │
                      │                                 └─►│ SIMD Vector Processor │ │                │
                      │                                    │ (Optimized for ML and │ │                │
                      │                                    │  signal processing)   │ │                │
                      │                                    └──────────────────────┘ │                │
                      │                                 │                           │                │
                      │                                 │  ┌──────────────────────┐ │                │
                      │                                 └─►│ 32-bit Scalar RISC   │ │                │
                      │                                    │ Processor (Scalar Unit│ │                │
                      │                                    └──────────────────────┘ │                │
                      └─────────────────────────────────────────────────────────────────────────────┘

                      - **SIMD Vector Processor**: Executes parallel vector operations for machine learning and signal processing.
                      - **Scalar Processing Unit**: Handles scalar operations and control flow.
                      - **Local Memory**: Provides fast access to data for the processors.
                      - **Memory Interface**: Manages data transfer between local and external memory.
                      - **Direct Memory Access (DMA)**: Automates data transfers without processor intervention.
                      - **Interconnects**: Facilitate communication with other AI Engine tiles and system components.
                      - **Control and Status Registers (CSR)**: Used for configuring and monitoring the AI Engine's state.
                      - **Instruction Cache**: Stores the instructions for the processors to reduce latency.
                      - **Event and Interrupt Controllers**: Manage events and interrupts for synchronization and communication.



                      The XDNA architecture is derived from AMD's acquisition of Xilinx, initially mirrored the spatial dataflow design of Xilinx Versal's AI Engine processors. The transition to XDNA2 brought enhancements tailored for Generative AI.


                      Code:
                      ┌─────────────────────┐    ┌─────────────────────┐    ┌────────────────────────┐
                      │  Xilinx Versal AI   │───►│   XDNA Architecture │───►│ XDNA2 with AI Enhancements │
                      │     Core (IP)       │    │ (AMD's Integration) │    │  (Optimized for Generative AI)  │
                      └─────────────────────┘    └─────────────────────┘    └────────────────────────┘

                      There's XRT driver for Linux systems, with AMD promise of ongoing development to provide a comprehensive software stack (time will tell, I'm cautionary and skeptical).

                      Code:
                      ┌───────────────┐    ┌─────────────┐    ┌─────────┐
                      │ Linux Kernel  │───►│ XRT Driver  │───►│  XDNA2  │
                      └───────────────┘    └─────────────┘    └─────────┘
                      The XRT driver bridges XDNA2 with Linux environments.

                      NPUs can be utilized for a variety of non-AI tasks. These include digital signal processing, image and video processing, and scientific simulations where parallel processing can lead to performance gains.

                      Code:
                      ┌─────────────────────────────────────────────────────────────────────────────┐
                      │                                   NPU                                       │
                      └─────────────────────────────────────────────────────────────────────────────┘
                            │                                │                             │
                            ▼                                ▼                             ▼
                      ┌──────────┐                   ┌─────────────────┐             ┌───────────┐
                      │ Digital  │                   │ Image & Video   │             │ Scientific│
                      │ Signal   │                   │ Processing      │             │ Simulations│
                      │ Processing│                   └─────────────────┘             └───────────┘
                      └──────────┘
                      NPUs are not limited to AI tasks and can enhance performance in various non-AI applications.

                      Development cycle for AI models includes training, conversion to ONNX format, quantization to INT8, compilation into `.xclbin` files, and execution on the NPU (XDNA2).

                      Code:
                      +─────────────+    +────────────────────+    +──────────────+    +──────────────+    +───────────+    +─────────────────────+    +──────────────+    +──────────────+
                      |  Training   | ──►| Conversion to ONNX | ──►| Quantization | ──►| Compilation  | ──►| .xclbin File |───►│ Executable AI Model │───►│ Optimization │───►│ NPU Execution │
                      |             |    | Format             |    | to INT8      |    | into .xclbin |    |             |    | (ONNX/Vitis AI)      |    |              |
                      +─────────────+    +────────────────────+    +──────────────+    +──────────────+    +───────────+    +─────────────────────+    +──────────────+    +──────────────+

                      Before deployment, AI applications undergo a crucial optimization phase through ONNX/Vitis AI, ensuring they run efficiently on the NPU.

                      Critical optimization steps that AI applications undergo for peak performance on the NPU.

                      The `.xclbin` file is the final, executable form of an AI model, ready to be processed by the NPU.

                      The `.xclbin` file enables execution on the NPU, representing the readiness of an AI model.


                      URLs
                      - Ryzen AI Software GitHub Repository: https://github.com/amd/RyzenAI-SW
                      - AMD Developer Resources for Ryzen AI Software: https://www.amd.com/en/developer/res...en-ai-software
                      - Ryzen AI Software Documentation Portal: https://ryzenai.docs.amd.com/en/latest/
                      - XRT Driver for Linux: https://github.com/amd/xdna-driver​
                      Last edited by timofonic; 07 June 2024, 12:48 AM.

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