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Linux Patch Pending To Fix Support For The Transmeta Crusoe CPU

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  • #51
    Originally posted by muncrief View Post

    I understand vladpetric.I don't agree with your method of communication, but understand that many embrace it, and am not offended by it.

    As the only thing that truly offends me is the suffering of humanity, and our continued allowance of it. But that is another subject that I discuss in "A Future of the Brave" on my archived website "".

    And of course everyone always believed it was impossible, but I had VHDL simulations proving everything I said was true. In fact the last few pages of the document have two waveforms from a Data Generator. I don't know for certain what happened to the last simulation output pages, as they numbered around 50, and are not even readable by the FrameMaker 4 installation I have in my KVM Windows XP VM. I suspect it's because I've not been able to get the Adobe Font Manager and Pantone software to work, but when I restored the document I was primarily concerned with the text and gave up fairly quickly.

    But I have all the VHDL code, libraries, and simulation code and settings for everything from Mimic to Thrust. And if I had to could convert them to work in modern simulators.

    However I suspect that, even if I did, no one would believe it.

    Just as so many times before, across the many failed inventions I created.

    Alright, so I need to ask - at what level did you simulate things? A VHDL where you have one single signal triggering changes in ~10k logic blocks in a single clock cycle (assuming GHz frequencies) will work in a high level simulation, but it won't with a simulation of a fully synthesized chip. If you did a full synthesis, please specify at a minimum what technology and clock frequency you used.

    There's at least two issues there (super simplified): signal propagation delays (RC delays, where R is the resistance of the wire, and C the residual capacitance of the input gate), and fan out. Problem btw is that with the most recent technologies, RC delays don't get better versus previous technologies (e.g., because thinner wires have increased resistivity ...)

    Of course, I am making assumptions about things. If I'm making the wrong assumptions, please correct them ...

    Now I don't actually think it's necessary to be able to reconfigure a full chip in a single cycle, but you did mention that.