New Intel Patch Series To Further Help Alder Lake / Hybrid CPUs On Linux

[drakonas777]

drakonas777

It's a direct response to AMD being "cool": since Zen 1 AMD fans have cheered that AMD offers MOAR cores and better MT scores.

Now that Intel offers insane MT performance, AMD fans have changed their tone and it's suddenly "give us more performant cores"! Well, you have your P-cores which are a lot faster than Zen 3. So, where's Intel wrong once again? They offer the best in class ST and MT performance and yet ... a hybrid architecture is useless? Logic has died.

I've not talked about power efficiency/consumption - Meteor Lake will likely address that. Also, where it matters ADL CPUs are as efficient if not more efficient than Zen 3:

https://www.techpowerup.com/review/i...-limits/8.html
https://www.igorslab.de/en/intel-cor...ugal-part-1/5/

You should tune down your fanboy emotions. I did not even mention AMD. Also I did not write that hybrid architecture is useless, so I have no clue what a fuck are you talking about.

Obviously it's not useless. It's economically optimal for intel to minimize die space in offering some "one size fits all" solution. I'm writing about practicality of hybrid x86 from the consumer point of view. Reality is for gaming it would be much more practical yo have more cache instead E cores. In contrast, for heavy MT load it would be more practical to have massive amount of E cores, for example, in the same die space you could have about 40E cores instead 8P + 8E configuration used currently. Either way you pay for non-optimal use of die space FOR YOU, YOUR USE CASE, kapish? That's the idea.

[birdie]

You think you're smarter than Intel engineers who designed ADL, many of whom have multiple PhD's. Why don't you go work for Intel and offer those P-only and E-only dies which are no longer universal unlike desktop ADLs which can run with flying colors both ST and MT workloads?

More P cores with more cache? Insane power consumption.
Just E cores? Will be ridiculed for ST performance which will be lower than Zen 2.

I'm not a fucking Intel fanboy, I have Ryzen 7 5800X in my desktop right fucking now. I guess many people here have gone insane worshipping AMD - they don't recognize people who are not jerking off to one company or another. I've also had Ryzen 7 3700X, AMD Athlon 5600+ EE and Sempron 3400+ CPUs. Can you imagine? It's now my fourth AMD CPU.

I'd also like to buy a laptop based on Ryzen 6800U but there's nothing to choose from. Ridiculously expensive laptops from HP and ASUS. Dell and Acer have none besides I don't like Acer, their quality recently has been abysmal.

[drakonas777]

You think you're smarter than Intel engineers who designed ADL, many of them have multiple PHD's. Why don't you go work for Intel and offer those P-only and E-only dies which are no longer universal unlike desktop ADLs which can run with flying colors both ST and MT workloads?

More P cores with more cache? Insane power consumption.
Just E cores? Will be ridiculed for ST performance which will be lower than Zen 2.

I'm not a fucking Intel fanboy, I have Ryzen 7 5800X in my desktop right fucking now. I guess many people here have gone insane worshipping AMD - they don't recognize people who are not jerking off to one company or another. I've also had Ryzen 7 3700X, AMD Athlon 5600+ EE and Sempron 3400+ CPUs. Can you imagine? It's now my fourth AMD CPU.

You are failing to understand my point. ADL makes a lot of sense from business point of view. I don't deny that.

Power consumption of more P cores (only +2 realistically) would not be insane if stock power settings were rational. PL2 is insane indeed though, and it will be more insane for Raptor Lake (~350W or so). That's another Intel trick for reviews.

Let's take a current 8P+8E config for example. Hypothetically, roughly speaking in about the same amount of die space you could have:
8P + more cache or
10P or
36-40E or
xE + better GPU/peripherals/accelerators or
xP + better GPU/peripherals/accelerators or
some other combination


Almost any use case would benefit more of one of these above instead 8P+8E with the price that some specific benchmarks would not look good. So of course, why manufacture more SKUs, when you can optimize cost to some non-optimal config which sort of covers everything, but is not optimal for anything.

[birdie]

So, you want to work for Intel, OK

[F.Ultra]

You think you're smarter than Intel engineers who designed ADL, many of whom have multiple PhD's. Why don't you go work for Intel and offer those P-only and E-only dies which are no longer universal unlike desktop ADLs which can run with flying colors both ST and MT workloads?

And how many PhD's did the Intel engineers have that thought that they could outsource the CPU scheduler from the CPU to the compiler (Itanium)? Creating a hybrid x86 with E-cores and P-cores is most likely a business decision and not an engineering decision, and if it was an engineering decision then it was probably more on the "wouldn't it be cool to create a hybrid system" than "this fixed a real world problem".

[birdie]

And how many PhD's did the Intel engineers have that thought that they could outsource the CPU scheduler from the CPU to the compiler (Itanium)? Creating a hybrid x86 with E-cores and P-cores is most likely a business decision and not an engineering decision, and if it was an engineering decision then it was probably more on the "wouldn't it be cool to create a hybrid system" than "this fixed a real world problem".

The the fruity Apple cult company also uses a hybrid uArch (Apple M1/M2) for their desktop devices. I wonder why people here are obsessed with attacking every Intel's decision while they weren't even the first to go along with it.

[NobodyXu]

Obviously it's not useless. It's economically optimal for intel to minimize die space in offering some "one size fits all" solution. I'm writing about practicality of hybrid x86 from the consumer point of view. Reality is for gaming it would be much more practical yo have more cache instead E cores. In contrast, for heavy MT load it would be more practical to have massive amount of E cores, for example, in the same die space you could have about 40E cores instead 8P + 8E configuration used currently. Either way you pay for non-optimal use of die space FOR YOU, YOUR USE CASE, kapish? That's the idea.

Hey not everybody uses their computer just for gaming, nor does they use it just for heavy MT.
Most of the people needs both single thread and multi-threading performance and sometimes one single application can requires both single and multi threading performance.

Having both will be ideal to speeding up compilation, due to dependency, not everything is multi-threaded.
For example, in cargo, multiple crates can be compiled in parallel, but compiling one single crate is almost single-thread.
When doing "cargo build", initially it will be massively multi-threaded, but after a while, it will soon become more single-threaded.

As you can see, ADL makes perfect sense in this case here.

[F.Ultra]

The cargo cult company also uses a hybrid uArch (Apple M1/M2) for their desktop devices. I wonder why people here are obsessed with attacking every Intel's decision while they weren't even the first to go along with it.

Don't pretend that there exists any abundance of love for Apple here. Also questioning the real world use case for hybrid x86 is not the same thing as "attacking every intel's decision". It also doesn't answer how many of those PhD:s where confident that the CPU scheduler could be better handled by a compiler.

There are a lot of talk about how this hybrid design should be great for heavy MT in this thread while the real world fact is that Intel have no plans to release any hybrid Xeon, there will just be only P-cores Xeons and only E-cores Xeons. So the server/enterprise industry is not at all interested in this (according to Intel).

[F.Ultra]

Hey not everybody uses their computer just for gaming, nor does they use it just for heavy MT.
Most of the people needs both single thread and multi-threading performance and sometimes one single application can requires both single and multi threading performance.

Having both will be ideal to speeding up compilation, due to dependency, not everything is multi-threaded.
For example, in cargo, multiple crates can be compiled in parallel, but compiling one single crate is almost single-thread.
When doing "cargo build", initially it will be massively multi-threaded, but after a while, it will soon become more single-threaded.

As you can see, ADL makes perfect sense in this case here.

If you are interested in heavy MT then the P-cores will accomplish this better than the E-cores anyway so this is not an argument for a hybrid design.

[bridgman]

And how many PhD's did the Intel engineers have that thought that they could outsource the CPU scheduler from the CPU to the compiler (Itanium)?

In fairness, during the time that Itanium and EPIC were being conceived (late 80's through early 90's) the majority view was that scheduling would continue to move from hardware into the compiler, as part of the whole RISC movement.

It wasn't until Itanium design was well underway that the first OOO microprocessors started to appear, and another couple of years passed before OOO processors became sufficiently wide and deep (and fast relative to memory) that hiding cache misses started to provide an obvious advantage over compiler-managed parallelism.

That said, it must have been a bit wierd working on Itanium during the late 90's... there's a Far Side comic where a bunch of dinosaurs are pointing at and laughing at a smaller animal with fur... and one of the dinosaurs is looking up and holding a (paw ?) out to catch the first flakes of snow.