CXL 3.0 Specification Released - Doubles The Data Rate Of CXL 2.0

[phoronix]

Phoronix: CXL 3.0 Specification Released - Doubles The Data Rate Of CXL 2.0

The CXL Consortium today announced the Compute Express Link 3.0 specification that doubles the data rate of CXL 2.0 to 64 GT/s while introducing no added latency...

https://www.phoronix.com/news/CXL-3....ation-Released

[coder]

In case anyone was wondering, CXL 1.0 and 2.0 both run atop the same PHY layer as PCIe 5.0. CXL 3.0 advances the PHY layer spec to that of PCIe 6.0 (among other things).

A major consequence of sharing the same PHY layer as PCIe is to make it easy for implementations to support both. It doesn't mean that consumer platforms with PCIe 5.0 will automatically support any version of CXL.

CXL can also be layered atop UCIe, for in-package chiplet-to-chiplet communication.

Anandtech has a good writeup of the new announcement, although their nice graphics (including a CXL version feature comparison) seem to be sourced from a CXL slide deck that I've yet to locate.

https://www.anandtech.com/show/17520...exible-fabrics

[coder]

In related news: CXL Consortium and OpenCAPI Consortium Sign Letter of Intent to Transfer OpenCAPI Specifications to CXL

Another tidbit I missed from earlier this year: CXL Consortium Signs Agreement with Gen-Z Consortium to Accept Transfer of Gen-Z Specifications and Assets

(insert joke about Gen-Z and asset transfers, here)
(probably also work in something about crypto or NFTs)

[Setif]

Does someone know if anyone has adapted CXL 1.0 or CXL 2.0?

[coder]

Does someone know if anyone has adapted CXL 1.0 or CXL 2.0?

Intel's upcoming (but delayed, yet again) Sapphire Rapids server CPUs will support CXL 1.1.

AMD's Genoa (Zen 4-based) EPYC will also support CXL 1.1.