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AMD Talks Up Zen 4 AVX-512, Genoa, Siena & More At Financial Analyst Day

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  • #21
    Originally posted by ddriver View Post
    There are flavors upon flavors of avx 512, it is really a mess, thanks intel. Some of the instructions are rather exotic and not that useful for general use. Intel itself most likely doesn't have and will not have a cpu that supports "all avx 512 instructions".
    That would be correct.

    I really hope Intel doesn't fragment the AMX instruction set the way they did AVX-512, although with the way they talk about it being "extensible"... I wouldn't bet money on it.

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    • #22
      Originally posted by rclark View Post
      Sounds great! Thanks for the news! But I wonder how many of us with make the 'jump' having to buy at least 'motherboard/memory/cpu' out the gate .[...] I did jump on the first Ryzen 1600 when introduced and just upgraded CPUs (which was 'very' nice trick with the AM4 socket), but then I was actually 'needing' better performance back then.
      Well, I bought the first Ryzen Hardware back when it was released (1800X). I'm considering going AM5 now.

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      • #23
        Originally posted by oleid View Post
        Well, I bought the first Ryzen Hardware back when it was released (1800X). I'm considering going AM5 now.
        Thank you brother! You make things cheaper for us late adopters

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        • #24
          Originally posted by ddriver View Post
          There are flavors upon flavors of avx 512, it is really a mess, thanks intel.
          Last time i wrote some AVX-256 Code i used their "Intrinsics Guide", they mix "real" instructions and operation implemented in their SVML lib there.. Doesn´t help either:
          https://www.intel.com/content/www/us...ide/index.html
          However you can get a pretty good look at the madness of different AVX512 "sets" of feature there, if you hover over the "AVX-512" thingy on the left side.
          If you work with GCC, all or most of the intrinsics which 1:1 map to an CPU instruction are there, but the intrinsics guide has some intrinsics which are implemented in their proprietary (SVML) lib are not.
          They are only availiable in their proprietary compiler or in newer MVCC versions it seems, otherwise you ahve to use MKL, but i might be wrong here.
          This just adds to the confusion IMHO.

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          • #25
            Originally posted by Spacefish View Post

            Last time i wrote some AVX-256 Code i used their "Intrinsics Guide", they mix "real" instructions and operation implemented in their SVML lib there.. Doesn´t help either:
            https://www.intel.com/content/www/us...ide/index.html
            However you can get a pretty good look at the madness of different AVX512 "sets" of feature there, if you hover over the "AVX-512" thingy on the left side.
            If you work with GCC, all or most of the intrinsics which 1:1 map to an CPU instruction are there, but the intrinsics guide has some intrinsics which are implemented in their proprietary (SVML) lib are not.
            They are only availiable in their proprietary compiler or in newer MVCC versions it seems, otherwise you ahve to use MKL, but i might be wrong here.
            This just adds to the confusion IMHO.
            If you want higher level functions over intrinsics, like SVML, and do not want to depend on a specific compiler, you may use libraries like Sleef https://sleef.org/.
            Compilers are not able, and will not be able, to deal with all the complexity of AVX-512 flavors, so the only way to take full advantage of it is to use intrinsics... and to know what you do. I have seen completely esoteric and inefficient codes with intrinsics...

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            • #26
              As long as AMD cannot provide any volume to the market, having the best CPU on the planet won't help them much to gain market share (by volume). Rembrandt notebooks are still not widely available in Europe, and as we have seen with Zen 3, they now charge a premium everywhere they can, that means no good for consumers until Intel gets competitive again.

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              • #27
                Originally posted by Linuxxx View Post
                So, will AVX-512 support mean all instructions are going to be implemented or only the ones benefitting AI/ML workloads?

                And will it be similar to first gen Zen 1 where AVX2 was realized as 2 × 128 bits wide registers, so maybe AVX-512 as 2 × 256 bits?

                According to WikiChip, Zen 4 will support the same AVX-512 instruction subsets as Ice Lake, together with the extra AVX-512 instructions of Cooper Lake.

                It will not support the AVX-512 instructions added by Tiger Lake or Sapphire Rapids.

                About the speed, nothing is certain, but it is likely that Zen 4 will do only one 512-bit FMA per cycle, but probably it will be able to also do a 512-bit FADD simultaneously with the FMA. This will result in a speed at equal clock frequency that is intermediate between the Intel models with one 512-bit FMA per cycle and the Intel models with two 512-bit FMA per cycle.

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                • #28
                  Originally posted by kobblestown View Post

                  Thank you brother! You make things cheaper for us late adopters
                  Well, I needed hardware since my old dev machine was broken...

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                  • #29
                    Originally posted by zamroni111 View Post
                    3nm euv will be very expensive foundry unless cheaper and more efficient euv laser generation is invented.
                    Low profit margin products, e.g. consumer cpu and gpu, might not be profitable enough to use it.
                    i won't be surprised if even apple don't use it for a and m soc.
                    That's not how things work at all. We are already using EUV NOW... 3nm will only decrease cost per transistor so literally everyone in the high performance segment of the market will want to use it as soon as possible. The cost of the EUV lasers is minuscule....

                    They only reason you'd use 5nm over 3nm... if both nodes are available is you've already taped out the 5nm design.

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                    • #30
                      Originally posted by shmerl View Post
                      What about 16-core CPUs with 3D V-cache?
                      One of the slides suggests that there will be Zen4, Zen4c and Zen4+VCache in high-performance desktop machines (Threadripper).

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