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AMD Posts New Linux Code For Zen 4's UAI Feature

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  • AMD Posts New Linux Code For Zen 4's UAI Feature

    Phoronix: AMD Posts New Linux Code For Zen 4's UAI Feature

    AMD posted this morning a new Linux kernel patch series for enabling a new feature for "upcoming processors" that is almost definitively for Zen 4, continuing their work in recent weeks around more open-source patches in preparing for their next-generation processors...

    https://www.phoronix.com/scan.php?pa...-Zen-4-Tagging

  • #2
    Oh FFS, it's the same as intels but ever so slightly different as to require a separate codepath. I'd reject both LAM and UAI until intel and amd have a compatible (same bits to enable/control/...) hardware implementation.

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    • #3
      uuh, if AMD defined it to not ignore upper address bits for SS, then compilers will have to learn to avoid default-SS-based addresses such as using RBP as a base pointer. this seems like an oversight.

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      • #4
        How this can be used in some software?

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        • #5
          Originally posted by dibal View Post
          How this can be used in some software?
          By using prctl, it sounds like.

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          • #6
            Interesting to see such an old idea come back. IIRC, the original Apple Macintosh OS used the high eight bits of 32-bit addresses to store flags or other information. This worked because the 68000 processor used 32-bit registers but only output the low 24 bits of addresses externally. Back then 16 megabytes was a lot of RAM. Later when the 68020 (or the 68030?) came along and exposed all 32 bits as address lines they had to update the OS to store those flags elsewhere.

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            • #7
              "128 million million kilobytes ought to be enough for anybody"
              Test signature

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              • #8
                Originally posted by Imroy View Post
                Interesting to see such an old idea come back. IIRC, the original Apple Macintosh OS used the high eight bits of 32-bit addresses to store flags or other information. This worked because the 68000 processor used 32-bit registers but only output the low 24 bits of addresses externally. Back then 16 megabytes was a lot of RAM. Later when the 68020 (or the 68030?) came along and exposed all 32 bits as address lines they had to update the OS to store those flags elsewhere.
                It came back long time ago on Arm64, and many people still use it on x86-64 although software needs to sign-extend the value manually, unlike the AArch64 hardware feature

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