Linux 5.17 AArch64 Code Has SME Preparations, Adds KCSAN Support

[phoronix]

Phoronix: Linux 5.17 AArch64 Code Has SME Preparations, Adds KCSAN Support

While the Linux 5.17 merge window hasn't opened up yet, there have been a few early pull requests sent out this week ahead of this imminent next kernel cycle. One of those already sent out is the ARM64/AArch64 CPU architecture code updates for Linux 5.17...

https://www.phoronix.com/scan.php?pa...x-5.17-AArch64

[tildearrow]

Typo?

- Clean=ups and preparations towards pringing

[elatllat]

The image is a 32 bit XU4, using an image of a C4 or N2 would be better.

[kylew77]

OK, I'll bite, How does, "Usage of SHA3 instructions for speeding up XOR." work? How does using a hashing algorithm speed up a logical gate operation? I had the basic undergrad computer architecture class and I thought XOR was implemented with an OR gate and a not gate on one of the two leads to the gate, simple enough? No?

[Jakobson]

OK, I'll bite, How does, "Usage of SHA3 instructions for speeding up XOR." work? How does using a hashing algorithm speed up a logical gate operation? I had the basic undergrad computer architecture class and I thought XOR was implemented with an OR gate and a not gate on one of the two leads to the gate, simple enough? No?

"Use the EOR3 instruction to implement xor_blocks() if the instruction is available, which is the case if the CPU implements the SHA-3 extension."
https://lore.kernel.org/all/[email protected]/T/