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AMD Makes Some Interesting SMCA Driver Changes For Future CPUs

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  • AMD Makes Some Interesting SMCA Driver Changes For Future CPUs

    Phoronix: AMD Makes Some Interesting SMCA Driver Changes For Future CPUs

    AMD is preparing updates to their SMCA (Scalable Machine Check Architecture) driver code for future CPUs and points to processors having different bank layouts between CPU cores on the package...

    https://www.phoronix.com/scan.php?pa...ferent-Layouts

  • #2
    It would be interesting if AMD (now that the company is going better) went back to the idea of a ARM variant of the Ryzen.

    It would also be interesting to see something radical different such as the Belt machine architecture.

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    • #3
      Can't say I'm a fan of Intel's asymmetric train-wreak.

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      • #4
        I'm extremely skeptical about asymmetric SMP or whatever wants to be called. To me, it's the inability to put more and better cores in the same CPU and a crap way to try to save power.

        I find it subpar in ARM, it seems the inability to make cores that scale well in power saving other than a "cool" idea.

        More cores, more bandwidth, more ram, ECC for everyone, more processing power... at less cost and less power consumption, that's what I want.

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        • #5
          Originally posted by timofonic View Post
          ECC for everyone
          ddr5 is "almost ecc" for everyone

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          • #6
            Originally posted by pal666 View Post
            ddr5 is "almost ecc" for everyone
            Not really. That's just chip-level ECC that's there to paper over the increased susceptibility to errors resulting from ever-denser DRAM dies. It's not link-level and I'm not sure it's even compulsory. I've also seen some suggestion that it's to enable lower much self-refresh rates, for the benefit of substantial idle/standby power-savings.

            Worse, because the channel-width of DDR5 is now halved to 32-bits (with each DIMM now providing 2 channels), you'll need 2 extra memory chips per DIMM to get a proper DDR5 DIMM with ECC. On the plus side, the level of protection should be even better, since you get 8 ECC bits per 32 data bits (instead of 8 per 64, like we've had in previous DIMM standards).
            coder
            Senior Member
            Last edited by coder; 06 December 2021, 06:09 PM.

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            • #7
              It's not even rumored that AMD will go hybrid. They've already announced Zen 4C (cloud) density cores to be used to reach 96-128 cores in their newer EPYCs.

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              • #8
                Originally posted by flashmozzg View Post
                It's not even rumored that AMD will go hybrid. They've already announced Zen 4C (cloud) density cores to be used to reach 96-128 cores in their newer EPYCs.
                I'm not quite sure what you mean, here. Are you saying they'll mix in some of the 4C cores with big cores in the same CPU?

                I think an intriguing first step would be for them to support mixing CPU types (i.e. Genoa, containing 96 regular Zen 4 cores + Bergamo, containing 128 Zen 4C) in dual-CPU setups. If that proves popular, then it would be worth them taking the next step and mixing the different chiplets within the actual CPU package. That experience should also give them some insight into what sort of ratios would be popular.

                Here's more on Genoa and Bergamo:

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                • #9
                  Originally posted by coder View Post
                  I'm not quite sure what you mean, here. Are you saying they'll mix in some of the 4C cores with big cores in the same CPU?

                  I think an intriguing first step would be for them to support mixing CPU types (i.e. Genoa, containing 96 regular Zen 4 cores + Bergamo, containing 128 Zen 4C) in dual-CPU setups. If that proves popular, then it would be worth them taking the next step and mixing the different chiplets within the actual CPU package. That experience should also give them some insight into what sort of ratios would be popular.

                  Here's more on Genoa and Bergamo:
                  For some reason I was sure it was demoed at that presentation, but I guess Zen5 + 4C are still only in the leaks (although very probable).
                  flashmozzg
                  Phoronix Member
                  Last edited by flashmozzg; 07 December 2021, 02:21 PM.

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                  • #10
                    Originally posted by coder View Post
                    I'm not quite sure what you mean, here. Are you saying they'll mix in some of the 4C cores with big cores in the same CPU?
                    The rumor is that Zen 5 chips will include 4C as little cores. We'll see. I think it's likely they'll all support the same instruction set, though, so it won't really be like Intel where they had to disable AVX512.

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