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  • #11
    Originally posted by coder View Post
    Ah, yes. For some reason, it didn't even occur to me they'd use V1 cores. I guess probably because I think of Graviton as their main cloud workhorse, whereas V-series seems like more of a HPC-type core.

    At the very least, I'd have expected them to use some special designation, like calling them Graviton 3c, because it'll be awkward when they introduce a N2-based CPU that further increases integer performance but actually reduces FPU (per-core, at least). And given the area- & power- efficiency advantages of N2, I'm sure it's coming.
    Here is some more info, it looks like a very interesting design with DDR controllers on separate chiplets, and all that performance at ~100W! Since Graviton 2 seems pretty good at HPC, I'd expect a much larger focus on HPC with Graviton 3. Note that N2 has ~10% lower integer performance than V1, so why would they ever want to switch to N2?

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    • #12
      Originally posted by PerformanceExpert View Post
      Note that N2 has ~10% lower integer performance than V1, so why would they ever want to switch to N2?
      Perf/W and Perf/mm2. Basically, $$$.

      Also, ARMv9 and SVE2.

      Edit: is that 10% lower IPC, or at the projected clock speed? Isn't V1 targeted at 7 nm, while N2 is targeted at 5 nm? It could probably clock 11% higher to compensate, and still deliver better perf/W.
      Last edited by coder; 02 December 2021, 11:27 AM.

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      • #13
        Originally posted by coder View Post
        Ah, yes. For some reason, it didn't even occur to me they'd use V1 cores. I guess probably because I think of Graviton as their main cloud workhorse, whereas V-series seems like more of a HPC-type core.

        At the very least, I'd have expected them to use some special designation, like calling them Graviton 3c, because it'll be awkward when they introduce a N2-based CPU that further increases integer performance but actually reduces FPU (per-core, at least). And given the area- & power- efficiency advantages of N2, I'm sure it's coming.
        My expectation (purely a guess!) is that
        - the big priority for G3 is the chiplet design (with getting SVE and v9 support into tools and OS a second-level concern)
        - and V1 gave them a six month time advantage over N2.
        Presumably, depending on what they conclude about the chiplet design, they'll either respin right away (using N2, new product in 6..9 months?) or wait 12..18 months and use N3.

        Two interesting things about the chiplet design suggest themselves:
        (a) the memory controllers are on separate chiplets. Given the extra area, are these "integrated" designs like Apple is using. The Apple design has the SLC as, essentially, a cache in front of the DRAM (as opposed to a cache on top of the L2's) with advantages in both how the cache interacts with the memory controller, and in how coherence is handled. Given extra chiplet area, you can replicate the Apple design with something serious like a 32MiB cache on each chiplet.

        (b) what's the win in using chiplets this way? The obvious idea that suggests itself is
        - CPU on 5nm (expensive, constrained, but highest performance/watt)
        - mem controller (+LLC?) on 7nm (cheaper, not much of a downside if most of your area is SRAM anyway)
        - PCIe IO on 16nm (large analog footprint)
        ?

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