Linux 5.14 Supports Some Exciting Features With RISC-V

[PerformanceExpert]

there is nothing in the ISA spec stopping an CPU to implementing it as efficient as x86. There will be however, a huge efficiency and compatbitiliy increase from the Vector extension compared to the incompatible mess that is MMX, 3dnow, SSE*, AVX* and all the crazy new advanced matrix stuff and in general non crazy variable length instructions ;-) https://www.youtube.com/watch?v=9e9LCYt3hoc

RISC-V was designed for tiny microcontrollers, and this makes it harder to implement a high performance core. Theoretically one could put x86 levels of money and effort into it, but let's be honest, that's never going to happen. Let's look at the facts: RISC-V existed for over 10 years, and so far nobody has made a fast RISC-V implementation. AArch64 is almost 11 years old and there are many fast implementations that compete with the best x86 implementations while being more efficient.

The RISC-V vector extension has been very slow going, and as a result there are now several incompatible vector extensions. Even when CPUs finally add the official vector extension, most code won't see any performance gains since all software has been built without vector extensions - and they remain optional. On x86_64 and AArch64 one can always rely on vector extensions being available - far better than having to fallback to a bare-bones ISA because all the useful instructions have been added into optional extensions.

[rene]

RISC-V was designed for tiny microcontrollers, and this makes it harder to implement a high performance core. Theoretically one could put x86 levels of money and effort into it, but let's be honest, that's never going to happen. Let's look at the facts: RISC-V existed for over 10 years, and so far nobody has made a fast RISC-V implementation. AArch64 is almost 11 years old and there are many fast implementations that compete with the best x86 implementations while being more efficient.

The RISC-V vector extension has been very slow going, and as a result there are now several incompatible vector extensions. Even when CPUs finally add the official vector extension, most code won't see any performance gains since all software has been built without vector extensions - and they remain optional. On x86_64 and AArch64 one can always rely on vector extensions being available - far better than having to fallback to a bare-bones ISA because all the useful instructions have been added into optional extensions.

RISCV is much junger than ARM which is nearly as old as x86. Obviously it takes some years to bootstrap a free and open instruction set architecture from scratch. Let's be honest, high performance RISCV is already happening, and you are not an PerformanceExpert ;-) rofl

[PerformanceExpert]

RISCV is much junger than ARM which is nearly as old as x86. Obviously it takes some years to bootstrap a free and open instruction set architecture from scratch. Let's be honest, high performance RISCV is already happening, and you are not an PerformanceExpert ;-) rofl

No, AArch64 is as old as RISC-V, and had to bootstrap from scratch as well. Being free and open hasn't exactly been an advantage, has it?

Name one high performance RISC-V implementation that does exist in the real world rather than on a powerpoint slide. I have a S21 Ultra in my hand here, there isn't a RISC-V CPU in silicon that can beat the slow little core in my phone.

[coder]

RISC-V was designed for tiny microcontrollers, and this makes it harder to implement a high performance core.

Really?

According to Jim Keller:

if I was just going to say if I want to build a computer really fast today, and I want it to go fast, RISC-V is the easiest one to choose. It’s the simplest one, it has got all the right features, it has got the right top eight instructions that you actually need to optimize for, and it doesn't have too much junk.

Theoretically one could put x86 levels of money and effort into it, but let's be honest, that's never going to happen. Let's look at the facts: RISC-V existed for over 10 years, and so far nobody has made a fast RISC-V implementation.

Until about 5 years ago, Intel had a fab advantage that made x86 untouchable, in the high-performance market segments.

AArch64 is almost 11 years old and there are many fast implementations that compete with the best x86 implementations while being more efficient.

The main reason being that the mobile revolution drove the mass porting of software to ARM. Hacker boards like Raspberry Pi didn't exactly hurt, either. So, if you were looking around to implement a new CPU, there was plenty of mature software support for ARM and IP blocks readily available. That's a recipe that didn't exist for anyone else. This accelerated the momentum of ARM.

RISC-V has been following a similar path, but it's just taking longer. Partly because ARM deprived it of some oxygen. However, I think Nvidia's purchase of ARM could be one of the best things to happen to RISC-V.

Even when CPUs finally add the official vector extension, most code won't see any performance gains since all software has been built without vector extensions - and they remain optional.

Huh? RISC-V for general purpose computing is still a ways off. There will be many new builds, optimizations, and tools development before then.

If we compare it with x86, AMD still doesn't even support any AVX-512 extensions, and Intel's own support for AVX-512 is a mess.

If we compare it with ARM, hardly anything supports SVE.

On x86_64 and AArch64 one can always rely on vector extensions being available - far better than having to fallback to a bare-bones ISA because all the useful instructions have been added into optional extensions.

I think we don't yet know which combinations of ISA extensions are going to dominate general-purpose computing with RISC-V. And x86 has been laying the groundwork for multiple ISA levels, which should enable more opportunistic optimizations to be loaded at runtime:

GNU C Library 2.33 Released With HWCAPS To Load Optimized Libraries For Modern CPUs

[Vistaus]

Most of the people in the world have an Android phone, and I believe freedom should be for everyone, not just tech giants who have freedom in their data center.

Why does Android matter so much to you? The vast majority of people doesn't even know what's powering their Android phone (or any phone, for that matter) anyway.

[coder]

No, AArch64 is as old as RISC-V, and had to bootstrap from scratch as well.

Not true. AArch64 had the momentum of the mobile revolution behind it. ARM, Google, Apple, Qualcomm, and others all pitched in to enable the software ecosystem support for it, because it gave them a path forward from AArch32.

RISC-V has also had a consortium behind it, but mostly of smaller players and others who are more interested in its long-term prospects and therefore not as deeply invested in quickly ramping it up to be a performance core.

Being free and open hasn't exactly been an advantage, has it?

Not in terms of quickly eclipsing everything else, no. It's still too early to write the history books on this chapter, and I think we also lack the visibility into licensable IP to know how fast RISC-V is dominating that market.

Name one high performance RISC-V implementation that does exist in the real world

Give it time. Someone could've said the same thing about ARM, years ago, or even x86. Some people thought x86 would never dominate the server/workstation segment.

[rene]

No, AArch64 is as old as RISC-V, and had to bootstrap from scratch as well. Being free and open hasn't exactly been an advantage, has it?

Name one high performance RISC-V implementation that does exist in the real world rather than on a powerpoint slide. I have a S21 Ultra in my hand here, there isn't a RISC-V CPU in silicon that can beat the slow little core in my phone.

I don't know if I should laugh or cry, however, participating in a threads like the is certainly a waste of time. AArch64 (a crappy name btw. shall we call it ARM64?) stands on the shoulders of two decades of ARM and a multi million if not billion $ company. There was also little "bootstrapping" as ARM was already well supported everywhere, ... Comparing that to a new and open process with individual startups that even need to work extra hard to avoid silicon patents is just laughable. Comparing flagship smartphone performance with startups that are happy they got their first working product out and shipping, ... What are you even frighted of? Your ARM shares? Everyone else should welcome open innovation for even better product innovation in the future.

[PerformanceExpert]

Not true. AArch64 had the momentum of the mobile revolution behind it. ARM, Google, Apple, Qualcomm, and others all pitched in to enable the software ecosystem support for it, because it gave them a path forward from AArch32.

The existing Arm ecosystem made things easier, but they still had to start from scratch since AArch64 is not backwards compatible with Arm or Thumb-2.

RISC-V has also had a consortium behind it, but mostly of smaller players and others who are more interested in its long-term prospects and therefore not as deeply invested in quickly ramping it up to be a performance core.

Much of the interest in RISC-V is in embedded uses, either by replacing in-house ISAs, ancient 8/16-bit ISAs or trying to save a few bucks on licensing/royalties. There seems to be far less interest for high performance uses.

Not in terms of quickly eclipsing everything else, no. It's still too early to write the history books on this chapter, and I think we also lack the visibility into licensable IP to know how fast RISC-V is dominating that market.

SiFive is basically using the same business model as Arm, MIPS, ARC and many others. Designing CPUs is expensive, so you obviously need to charge licensing fees and royalties. At that point whether the ISA itself is open or free doesn't matter.

Give it time. Someone could've said the same thing about ARM, years ago, or even x86. Some people thought x86 would never dominate the server/workstation segment.

The question is not whether it is theoretically possible but whether it makes sense. What would a high performance RISC-V add that couldn't be done by x86 or Arm today? Why spend hundreds of millions on designing a high performance RISC-V when you could license a faster Arm core for a fraction of the cost and risks? Nobody is willing to pay that much extra just because the ISA is open, so I think RISC-V has a slow uphill battle ahead.

[PerformanceExpert]

I don't know if I should laugh or cry, however, participating in a threads like the is certainly a waste of time. AArch64 (a crappy name btw. shall we call it ARM64?) stands on the shoulders of two decades of ARM and a multi million if not billion $ company. There was also little "bootstrapping" as ARM was already well supported everywhere, ... Comparing that to a new and open process with individual startups that even need to work extra hard to avoid silicon patents is just laughable. Comparing flagship smartphone performance with startups that are happy they got their first working product out and shipping, ... What are you even frighted of? Your ARM shares? Everyone else should welcome open innovation for even better product innovation in the future.

It's certainly a waste of time posting if you can't separate facts from fiction. So you now agree there are no high performance RISC-V cores... Designing a decent CPU is hard, time consuming and expensive - I'm sure various RISC-V startup have figured that out. Having an open ISA or not doesn't make much difference.

Note I wasn't comparing with Arm's flagship Cortex-X1 but with the slow little core. According to Geekbench 5, Cortex-X1 is about 20 times faster than the fastest RISC-V core listed. That gap takes a decade of 35% yearly gains to catch up... That makes RISC-V mobile phones a pipedream.

As for innovation, an open ISA or implementation is not new or innovative. And RISC-V is like 1980's barebones MIPS with minor changes, where is the innovation?

[rene]

It's certainly a waste of time posting if you can't separate facts from fiction. So you now agree there are no high performance RISC-V cores... Designing a decent CPU is hard, time consuming and expensive - I'm sure various RISC-V startup have figured that out. Having an open ISA or not doesn't make much difference.

Note I wasn't comparing with Arm's flagship Cortex-X1 but with the slow little core. According to Geekbench 5, Cortex-X1 is about 20 times faster than the fastest RISC-V core listed. That gap takes a decade of 35% yearly gains to catch up... That makes RISC-V mobile phones a pipedream.

As for innovation, an open ISA or implementation is not new or innovative. And RISC-V is like 1980's barebones MIPS with minor changes, where is the innovation?

I agree with nothing you write Mr FictionExpert :-/ ARM employee?