Originally posted by uid313
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Also the openCores/OpenRISC project in general has a lot of useful IP outside the core to help build more open SoC's or periphial devices in general. Wishbone is basically the only open cor BUS available and ready to go. Litex currently support 2 different risc-v cores, and more will likely follow. I'm just assuming mor1kx is the most stable or most familiar to the patch author.
And if Litex is a popular enough platform, Microwatt and LEON3 could be added. This isn't locked into any particular ISA or core.
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