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AMD EPYC 7003 "Milan" Linux Benchmarks - Superb Performance

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  • generousjack
    replied
    this is a great test. well done to phoronix Team.
    i am wonder how will be the test between Intel 5220R 2P, 6226R 2P with AMD EPYC 2P 7313,7453,7453

    since these are at the price range of USD1300 to USD1500 Price range per socket.

    eventually AMD 1st 2nd gene single thread performance always unable to match with Intel 5220R/6226R, this is crucial for virtual firewall appliance that license per vcpu on virtualization environment.

    this wil let consumer to decide which to go when choosing the right processor at this price range.

    thanks again for the great benchmark article


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  • coder
    replied
    Originally posted by bridgman View Post
    Not sure if it hurts or helps your argument, but both Zen2 and Zen3 used 7nm for the CPU chiplets and so Zen2 was the die shrink.
    FWIW, let's not forget that the Ryzen 3000XT-series introduced low-level process refinements that probably qualify as a "+", in Intel's manufacturing parlance.

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  • Jumbotron
    replied
    Originally posted by bridgman View Post

    Not sure if it hurts or helps your argument, but both Zen2 and Zen3 used 7nm for the CPU chiplets and so Zen2 was the die shrink.
    Thank you for the correction. I had forgotten that in my stream of thought. And let me clear, my equating Intel's "Tick Tock" CPU arch. cycle with AMD is a rough analogy to be sure. But I think even its "roughness" it still applies pretty well. So with the correction that Zen 2 was 7nm AND was a BIG arch improvement over Zen and Zen+ then I still stand by the notion that Zen 2 was a "Tock" and Zen 3, PARTICULARLY now knowing it was not a die shrink of Zen 2, still is as I stated above an "enhanced "Tock" to use Intel parlance. And as it was noted by Intel itself an enhanced " Tock" cadence was bestowed upon an existing microarch that could not be shrunk at the time but had some tweaks to the previous arch. but NOT enough to consider it a new arch. And that's my opinion of Zen 3.

    Ergo I think my argument stands firm that Zen 4 WILL BE a new arch in the Zen family. A full blown "Tock". It really has to be. The CCXs and Cache complex alone has to be significantly changed and reordered to take full advantage of Infinity Architecture 3.0, not to mention interoperability with CCIX for Xlinx and GenZ for tying racks together with Cache Coherency as well.

    Also to get greater IPC and aggregate performance uplift at the same core count AND same core clock of Zen 3 than Zen 3 got over Zen 2 requires very significant arch. changes. Much more so than Zen 3 over Zen 2. Once again making Zen 4 a "Tock" type arch advancement.

    AMD has to do this for Zen 4 at 5nm. If for nothing else than for Zen 4 to be the new arch. to get Zen 5 to 3nm. Because it's over for x86 at 3nm. After that, by 2030, I can see an entire motherboard being covered by chiplets with 3D embedded MRAM in place of DDR and SSDs being replaced with Optane like or Zram like storage. In other words...every PC will be HP's "The Machine". Because you won't be able to get performance uplift by shrinking the CPU or GPU anymore once you hit 3nm. Why? Physics. And Quantum Physics at that. Your data will just Quantum Physically tunnel out past 3nm.
    Last edited by Jumbotron; 17 March 2021, 02:27 AM.

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  • bridgman
    replied
    Originally posted by Jumbotron View Post
    Zen 3 COULD be considered either a "Tick" as it is a die shrink to 7nm. Or it COULD be considered an enhanced "Tock" of Zen 2 as Zen 3 did unify Zen 2 CCXs and L3 cache amongst other arch tweaks.
    Not sure if it hurts or helps your argument, but both Zen2 and Zen3 used 7nm for the CPU chiplets and so Zen2 was the die shrink.

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  • torsionbar28
    replied
    Originally posted by mppix View Post
    Says who?
    The PCIe5 folks, apparently. They've upped the power requirements, and it's above the published limit in the M.2 connector specifications. Ergo, you will not have PCIe5 M.2 devices.

    Originally posted by mppix View Post
    ... and if usb-c or PoE+ is any indication, we can do a lot of things for higher power + better power management over popular connectors...
    Not sure what you're saying here? That the industry will develop some future iteration of M.2 that is different from the current spec, and is able to carry PCIe5? Yes, I agree, they will have to, I believe we're saying the same thing here.

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  • mppix
    replied
    Originally posted by torsionbar28 View Post
    Honestly I'm more looking forward to what the storage technology will be for PCIe5 boards, at least on the client side. The M.2 connector does not carry enough electrical power to meet the PCIe5 spec...
    Says who?
    ... and if usb-c or PoE+ is any indication, we can do a lot of things for higher power + better power management over popular connectors...

    Leave a comment:


  • mppix
    replied
    Originally posted by Jumbotron View Post

    Simple deduction from previous cpu architectural history, both Intel and AMD, open source reporting and Lisa Su herself intimating that Zen 4 would be so refined over Zen 2 & 3 as to be considered a new arch.

    So..let's explore. Intel was famous until 14nm for their "Tick Tock" architecture advancement. The "Tick" was actually the die shrink and process enhancement of the previous "Tock" architecture change. Once Intel hit the 10nm brick wall they introduced an extended "Tock" enhancenent to existing architectures as the "Tick" die shrink broke down. And even these "Tock" enhancements became running jokes at Intel.

    Along comes AMD who was stuck at 28nm for years with a completely worn out and moribund "Dozer/Driver" arch. So they implemented a MASSIVE clean sheet "Tock" architecture redesign with Zen. Zen+ is their "Tick". Zen 2 is another "Tock". Not a completely new clean sheet redesign from Zen or Zen+. But enough to be considered "new" microarch. Zen 3 COULD be considered either a "Tick" as it is a die shrink to 7nm. Or it COULD be considered an enhanced "Tock" of Zen 2 as Zen 3 did unify Zen 2 CCXs and L3 cache amongst other arch tweaks. Zen 3 also has a tweaked Infinity Fabric interconnect now improved enough to be called Infinity Architecture. But there still is no complete connection to everything, CPUs, GPUs, DSPs, FPGAs, NPUs, etc with full DMA and full cache coherency. And Zen 3 and Zen 2 and Zen+ and Zen and even Bristol Ridge, the last of the Dozer/Driver CPU's are still on AM4 sockets with DDR-4 memory and PCI 4.

    Not Zen 4. First of all, Zen 4 needs a new socket as it will need DDR-5 and PCI 5. Second, Zen 4 will be connected to the full blown Infinity Architecture 3.0 with full DMA and Cache Coherency to all parts. Every CCX (and I suspect the CCX is going away) all Cache nodes, AI subprocessers, up to eight RDNA 3 and/or CDNA 3 GPUs per cabinet and more will independently communicate with zero memory copy. HSA will finally arrive nearly 15 years late.

    In addition, word is from inside AMD that early engineering samples of the Zen 4 based Genoa are generating 29% higher IPC and 40% higher aggregate performance uplift over Milan at the SAME core count and the SAME clock speed of Milan. You don't get that from simply moving down from 7nm to 5nm. You don't get that simply from moving from DDR-4 to DDR-5. You don't get that from simply tweaking CCXs and cache.

    You get that from a new architecture. A for real "Tock". Not a "Tick" shrink. Not a fake Intel like "Tock" enhancement that's so small it can't really be considered a new arch.

    Viewed in it's entirety, Zen 4 will be a new architecture on a new platform.
    What exactly is a new microarch?
    Intel and AMD cores are rarely "new"; they just optimize it... Intel tick-tok prioritized architecture optimizations one time and then die shrink the other time. Intel "core" could qualify so could AMD Zen and RDNA. The rest is more or less optimization.
    DDR5, pci5, infinity fabric, is "just" I/O. You could essentially get the same Zen3 cores on a smaller node. Don't get me wrong, porting Zen3 cores to 5nm could get you really good cores with reduced silicon area, up to 50% power savings, 25% faster or a combination thereof...
    Last edited by mppix; 16 March 2021, 05:00 PM.

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  • msroadkill612
    replied
    Originally posted by [email protected] View Post
    Benchmarks aside, Intel can still count on "settled-in-their-ways" system admins to continue to sell their stuff. Paraphrasing IBM, "nobody was fired for buying Intel".

    If things comes to worse, they can still lower their prices, just like AMD had to do on the Bulldozer era. It must have be anything but fun to be a Intel sales rep nowadays. A couple years ago, they could simply tell their clients this is the price, because we said so. Now they had to actually open their mouths and try convince some people not to change to AMD.
    Thats getting a bit past its use by date. When glaciers break, they do it big. Intel is laughably behind on so many metrics in the hard nosed business of servers, thatthe most cursory selection process is bound to hit a deal breaker.

    That said, i suspect the inarguable killer argument will be massively converged infrastructure. Despite the scary name, its simpler, cheaper & ~seamlessly expandable. its sorta the same magic that has won amd a succession of exaserver contracts, & much of it comes down to the quality & speed of the inter host connections. Its the new black, & intel is out classed by a big factor.

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  • Mike Frett
    replied
    I look forward to our new RISC overlords.

    Leave a comment:


  • coder
    replied
    Originally posted by Jumbotron View Post
    word is from inside AMD that early engineering samples of the Zen 4 based Genoa are generating 29% higher IPC and 40% higher aggregate performance uplift over Milan at the SAME core count and the SAME clock speed of Milan.
    Sounds like you're reading/believing too many of those rumor-mill sites.

    I say: keep your expectations low, and you won't be disappointed. Also, you'll write better code, because you're not expecting ever-faster hardware to bail you out.

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