AMD EPYC 7003 "Milan" Linux Benchmarks - Superb Performance

[cjcox]

Intel bring backs the Blue Man Group in a last ditch effort....

[willmore]

I must have missed it, but what does the "P" suffix indicate? I see all the same specs, but they're slighly cheaper.

[torsionbar28]

I must have missed it, but what does the "P" suffix indicate? I see all the same specs, but they're slighly cheaper.

A "P" suffix denotes support for only a single socket configuration.

[angrypie]

You must be too young to remember Itanium...

Yeah, but Itanic was so appalling nobody even pretended to like it. The Intel 64 Xeons at least had respectable performance, but they've been obsolete since even 1st gen Epyc.

[smitty3268]

Not only that, some public cloud providers such as Microsoft Azure are even launching new AMD EPYC Milan cloud instances today...

That's where all the 5950x chiplets have gone...

[smitty3268]

Settle down snowflake. You too syxbit. I totally stand by my statement. Because it's true. Zen was a revolution over the "Dozer/Driver" CPU's. Zen+ was just an iteration and just a slight process iteration at that. Zen 2 was a big evolutionary jump up from both Zen and Zen+. But Zen 3 and thus Milan is NOT AS BIG an evolutionary step up from Zen 2 as Zen 2 was from Zen and Zen+, much less Zen from "Dozer/Driver".

However, Zen 4 and thus Genoa along with Infinity Architecture 3, DDR 5 and PCI 5 along with RDNA 3 and 4 and CDNA 3 and 4 WILL be revolutionary. Zen 4 IS a new arch. Zen 4 WILL NOT be an evolutionary refinement to Zen 3.

No one is arguing with any of that. What you said that's dumb was

Just what Zen 2 and Rome should have been

Anyway, Zen 3 actually is a fairly big deal for AMD in the server space, in that they finally have a chip that wins hands down on single-threaded tasks. That's not something everyone cares about, but it is a big deal for a subset of the market. It's entirely possible Zen 4 will actually be less impressive vs the competition than Zen 3 is, if Intel can get it's house in order by then.

[mppix]

However, Zen 4 and thus Genoa along with Infinity Architecture 3, DDR 5 and PCI 5 along with RDNA 3 and 4 and CDNA 3 and 4 WILL be revolutionary.

Sure, we all look forward to a DDR5 + PCIe5 CPU possibly with 128cores on 5nm. However as you point out quite a bit of software evolution is needed to make it count the most.

Zen 4 IS a new arch. Zen 4 WILL NOT be an evolutionary refinement to Zen 3.

How do you know that?

[torsionbar28]

Yeah, but Itanic was so appalling nobody even pretended to like it.

HP dumped PA-RISC and Alpha for it. SGI dumped MIPS for it. I'd say that's more than pretending. And both paid a hefty price for hitching their wagon to the wrong horse. Sun ported Solaris to Itanium, but it took them so long, by the time it was ready, the writing was on the wall and they wisely never released it.

[torsionbar28]

Sure, we all look forward to a DDR5 + PCIe5 CPU possibly with 128cores on 5nm.

Honestly I'm more looking forward to what the storage technology will be for PCIe5 boards, at least on the client side. The M.2 connector does not carry enough electrical power to meet the PCIe5 spec...

[Jumbotron]

Sure, we all look forward to a DDR5 + PCIe5 CPU possibly with 128cores on 5nm. However as you point out quite a bit of software evolution is needed to make it count the most.


How do you know that?

Simple deduction from previous cpu architectural history, both Intel and AMD, open source reporting and Lisa Su herself intimating that Zen 4 would be so refined over Zen 2 & 3 as to be considered a new arch.

So..let's explore. Intel was famous until 14nm for their "Tick Tock" architecture advancement. The "Tick" was actually the die shrink and process enhancement of the previous "Tock" architecture change. Once Intel hit the 10nm brick wall they introduced an extended "Tock" enhancenent to existing architectures as the "Tick" die shrink broke down. And even these "Tock" enhancements became running jokes at Intel.

Along comes AMD who was stuck at 28nm for years with a completely worn out and moribund "Dozer/Driver" arch. So they implemented a MASSIVE clean sheet "Tock" architecture redesign with Zen. Zen+ is their "Tick". Zen 2 is another "Tock". Not a completely new clean sheet redesign from Zen or Zen+. But enough to be considered "new" microarch. Zen 3 COULD be considered either a "Tick" as it is a die shrink to 7nm. Or it COULD be considered an enhanced "Tock" of Zen 2 as Zen 3 did unify Zen 2 CCXs and L3 cache amongst other arch tweaks. Zen 3 also has a tweaked Infinity Fabric interconnect now improved enough to be called Infinity Architecture. But there still is no complete connection to everything, CPUs, GPUs, DSPs, FPGAs, NPUs, etc with full DMA and full cache coherency. And Zen 3 and Zen 2 and Zen+ and Zen and even Bristol Ridge, the last of the Dozer/Driver CPU's are still on AM4 sockets with DDR-4 memory and PCI 4.

Not Zen 4. First of all, Zen 4 needs a new socket as it will need DDR-5 and PCI 5. Second, Zen 4 will be connected to the full blown Infinity Architecture 3.0 with full DMA and Cache Coherency to all parts. Every CCX (and I suspect the CCX is going away) all Cache nodes, AI subprocessers, up to eight RDNA 3 and/or CDNA 3 GPUs per cabinet and more will independently communicate with zero memory copy. HSA will finally arrive nearly 15 years late.

In addition, word is from inside AMD that early engineering samples of the Zen 4 based Genoa are generating 29% higher IPC and 40% higher aggregate performance uplift over Milan at the SAME core count and the SAME clock speed of Milan. You don't get that from simply moving down from 7nm to 5nm. You don't get that simply from moving from DDR-4 to DDR-5. You don't get that from simply tweaking CCXs and cache.

You get that from a new architecture. A for real "Tock". Not a "Tick" shrink. Not a fake Intel like "Tock" enhancement that's so small it can't really be considered a new arch.

Viewed in it's entirety, Zen 4 will be a new architecture on a new platform.