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AMD EPYC 7003 "Milan" Linux Benchmarks - Superb Performance

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  • #31
    Originally posted by [email protected] View Post
    It must have be anything but fun to be a Intel sales rep nowadays. A couple years ago, they could simply tell their clients this is the price, because we said so. Now they had to actually open their mouths and try convince some people not to change to AMD.
    Eh, the problem with buying AMD is the wait times. Their wafer allocation from TSMC is far less than Intel's production capacity, so you can actually obtain most Intel CPUs quicker & more easily (especially the higher-margin parts). If demand weren't so insane, lately, Intel would have some serious problems on its hands.

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    • #32
      Originally posted by torsionbar28 View Post
      SGI dumped MIPS for it.
      I can't say you're wrong about that, but I definitely remember SGI made their first x86-based workstation before Itanium even launched.

      Originally posted by torsionbar28 View Post
      Sun ported Solaris to Itanium, but it took them so long, by the time it was ready, the writing was on the wall and they wisely never released it.
      Sun also embraced Opteron, very quickly. I think I saw an AMD-based 2U Sun server in 2003?

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      • #33
        Originally posted by torsionbar28 View Post
        Honestly I'm more looking forward to what the storage technology will be for PCIe5 boards, at least on the client side. The M.2 connector does not carry enough electrical power to meet the PCIe5 spec...
        You're too optimistic, thinking client machines will even get PCIe 5. As for servers, they already have new SSD form factors, like the infamous "ruler".

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        • #34
          Originally posted by Jumbotron View Post
          word is from inside AMD that early engineering samples of the Zen 4 based Genoa are generating 29% higher IPC and 40% higher aggregate performance uplift over Milan at the SAME core count and the SAME clock speed of Milan.
          Sounds like you're reading/believing too many of those rumor-mill sites.

          I say: keep your expectations low, and you won't be disappointed. Also, you'll write better code, because you're not expecting ever-faster hardware to bail you out.

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          • #35
            I look forward to our new RISC overlords.

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            • #36
              Originally posted by [email protected] View Post
              Benchmarks aside, Intel can still count on "settled-in-their-ways" system admins to continue to sell their stuff. Paraphrasing IBM, "nobody was fired for buying Intel".

              If things comes to worse, they can still lower their prices, just like AMD had to do on the Bulldozer era. It must have be anything but fun to be a Intel sales rep nowadays. A couple years ago, they could simply tell their clients this is the price, because we said so. Now they had to actually open their mouths and try convince some people not to change to AMD.
              Thats getting a bit past its use by date. When glaciers break, they do it big. Intel is laughably behind on so many metrics in the hard nosed business of servers, thatthe most cursory selection process is bound to hit a deal breaker.

              That said, i suspect the inarguable killer argument will be massively converged infrastructure. Despite the scary name, its simpler, cheaper & ~seamlessly expandable. its sorta the same magic that has won amd a succession of exaserver contracts, & much of it comes down to the quality & speed of the inter host connections. Its the new black, & intel is out classed by a big factor.

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              • #37
                Originally posted by Jumbotron View Post

                Simple deduction from previous cpu architectural history, both Intel and AMD, open source reporting and Lisa Su herself intimating that Zen 4 would be so refined over Zen 2 & 3 as to be considered a new arch.

                So..let's explore. Intel was famous until 14nm for their "Tick Tock" architecture advancement. The "Tick" was actually the die shrink and process enhancement of the previous "Tock" architecture change. Once Intel hit the 10nm brick wall they introduced an extended "Tock" enhancenent to existing architectures as the "Tick" die shrink broke down. And even these "Tock" enhancements became running jokes at Intel.

                Along comes AMD who was stuck at 28nm for years with a completely worn out and moribund "Dozer/Driver" arch. So they implemented a MASSIVE clean sheet "Tock" architecture redesign with Zen. Zen+ is their "Tick". Zen 2 is another "Tock". Not a completely new clean sheet redesign from Zen or Zen+. But enough to be considered "new" microarch. Zen 3 COULD be considered either a "Tick" as it is a die shrink to 7nm. Or it COULD be considered an enhanced "Tock" of Zen 2 as Zen 3 did unify Zen 2 CCXs and L3 cache amongst other arch tweaks. Zen 3 also has a tweaked Infinity Fabric interconnect now improved enough to be called Infinity Architecture. But there still is no complete connection to everything, CPUs, GPUs, DSPs, FPGAs, NPUs, etc with full DMA and full cache coherency. And Zen 3 and Zen 2 and Zen+ and Zen and even Bristol Ridge, the last of the Dozer/Driver CPU's are still on AM4 sockets with DDR-4 memory and PCI 4.

                Not Zen 4. First of all, Zen 4 needs a new socket as it will need DDR-5 and PCI 5. Second, Zen 4 will be connected to the full blown Infinity Architecture 3.0 with full DMA and Cache Coherency to all parts. Every CCX (and I suspect the CCX is going away) all Cache nodes, AI subprocessers, up to eight RDNA 3 and/or CDNA 3 GPUs per cabinet and more will independently communicate with zero memory copy. HSA will finally arrive nearly 15 years late.

                In addition, word is from inside AMD that early engineering samples of the Zen 4 based Genoa are generating 29% higher IPC and 40% higher aggregate performance uplift over Milan at the SAME core count and the SAME clock speed of Milan. You don't get that from simply moving down from 7nm to 5nm. You don't get that simply from moving from DDR-4 to DDR-5. You don't get that from simply tweaking CCXs and cache.

                You get that from a new architecture. A for real "Tock". Not a "Tick" shrink. Not a fake Intel like "Tock" enhancement that's so small it can't really be considered a new arch.

                Viewed in it's entirety, Zen 4 will be a new architecture on a new platform.
                What exactly is a new microarch?
                Intel and AMD cores are rarely "new"; they just optimize it... Intel tick-tok prioritized architecture optimizations one time and then die shrink the other time. Intel "core" could qualify so could AMD Zen and RDNA. The rest is more or less optimization.
                DDR5, pci5, infinity fabric, is "just" I/O. You could essentially get the same Zen3 cores on a smaller node. Don't get me wrong, porting Zen3 cores to 5nm could get you really good cores with reduced silicon area, up to 50% power savings, 25% faster or a combination thereof...
                Last edited by mppix; 16 March 2021, 05:00 PM.

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                • #38
                  Originally posted by torsionbar28 View Post
                  Honestly I'm more looking forward to what the storage technology will be for PCIe5 boards, at least on the client side. The M.2 connector does not carry enough electrical power to meet the PCIe5 spec...
                  Says who?
                  ... and if usb-c or PoE+ is any indication, we can do a lot of things for higher power + better power management over popular connectors...

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                  • #39
                    Originally posted by mppix View Post
                    Says who?
                    The PCIe5 folks, apparently. They've upped the power requirements, and it's above the published limit in the M.2 connector specifications. Ergo, you will not have PCIe5 M.2 devices.

                    Originally posted by mppix View Post
                    ... and if usb-c or PoE+ is any indication, we can do a lot of things for higher power + better power management over popular connectors...
                    Not sure what you're saying here? That the industry will develop some future iteration of M.2 that is different from the current spec, and is able to carry PCIe5? Yes, I agree, they will have to, I believe we're saying the same thing here.

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                    • #40
                      Originally posted by Jumbotron View Post
                      Zen 3 COULD be considered either a "Tick" as it is a die shrink to 7nm. Or it COULD be considered an enhanced "Tock" of Zen 2 as Zen 3 did unify Zen 2 CCXs and L3 cache amongst other arch tweaks.
                      Not sure if it hurts or helps your argument, but both Zen2 and Zen3 used 7nm for the CPU chiplets and so Zen2 was the die shrink.
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