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Apple M1 ARM Performance With A 2020 Mac Mini

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  • #91
    Leave it to Phoronix readers to gripe about everything. I get it, Apple's closed nature sucks, but you have to get real for a moment: this is some absurdly good performance for an ARM chip. Even Rosetta 2 managed to have comparable (sometimes better) performance than a 6c/12t Intel chip and uses 1/6 the power.

    While you Stallmanites whine about the lack of source code that you were never going to touch in the first place, I will applaud Apple for taking micro-optimizations seriously, in a world where software development just throws more system resources at problems instead of actually trying to solve them.

    I'm not going to buy this (never bought an Apple product my whole life) but at least I have the maturity to know good engineering when I see it.
    Last edited by schmidtbag; 21 November 2020, 11:05 AM.

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    • #92
      Originally posted by PerformanceExpert View Post

      It outperforms the fastest x86 desktops including Zen 3 at a fraction of the power. The only conclusion: game over.
      Sure, keep playing IPhone games

      https://www.youtube.com/watch?v=bdQ7u0mR570

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      • #93
        Originally posted by BillBroadley View Post

        I'm guessing here. But the M1 does have an unusually large L1 cache. My bet is the ZSTD has some heavily used table that fits in the L1 cache of the M1 and does not fit in the cache for the other CPUs. The result is an anomalously high result for the m1 that's not representative of most codes.
        M1 L1 data cache is said to be 128 KB per core. It's not that crazy high.

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        • #94
          TSMC 5nm + a company that knows what they are doing.

          Man, am I looking forward to Zen4 with ddr5, pcie5, and pretty please 128 cores.

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          • #95
            Originally posted by evergreen View Post

            M1 L1 data cache is said to be 128 KB per core. It's not that crazy high.
            AMD is 32KB L1, Intel is 48KB. A 64KB-128KB datastructure that was used heavily would HEAVILY favor the M1.

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            • #96
              What's the associativity of their L1 caches, and is 16K the minimum page size? I'm wondering if they are simply dealing with aliasing or are able to avoid that with a larger page size.

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              • #97
                Hi Michael,

                I hope you can make some hpc benchmarks natively on the mac mini m1. I'm really curious to know how well it performs in those tasks compared to x86. It would also have been nice if you had some results from a similar "nuc" system with a ryzen 9 4800U, but I guess that's too much.

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                • #98
                  Originally posted by Anarchy View Post
                  Hi Michael,

                  I hope you can make some hpc benchmarks natively on the mac mini m1. I'm really curious to know how well it performs in those tasks compared to x86. It would also have been nice if you had some results from a similar "nuc" system with a ryzen 9 4800U, but I guess that's too much.
                  More benchmarks are coming but I don't have any modern NUC like system nor any Ryzen 4800/4900 series hardware.
                  Michael Larabel
                  http://www.michaellarabel.com/

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                  • #99
                    Originally posted by evergreen View Post

                    M1 L1 data cache is said to be 128 KB per core. It's not that crazy high.

                    Wrong.

                    The M1 has 8 CPU cores. 4 High Performance Cores. 4 Low Power Cores.

                    Each of the 4 High Performance Cores has 320 KB of L1 Cache. There is 192 KB of L1 Data Cache. And 128 KB of L1 Instruction Cache. Total L1 cache is 320 KB.

                    So at 4 cores x 320 KB of combined L1 Cache = 1.28 MB of L1 Cache for the High Performace Cores.


                    Now...as mentioned earlier, there are also 4 Low Power Cores in the M1.

                    Each of the 4 Low Power Cores has 192 KB of L1 Cache. There is 128 KB of L1 Data Cache. And 64 KB of L1 Instruction Cache. Total L1 Cache is 192 KB.

                    So at 4 cores x 192 KB of combined L1 Cache = 768 KB of L1 Cache for the Low Power Cores.

                    So....the TOTAL COMBINED PHYSICAL ON DIE L1 Cache in each and every Apple Silicon M1 SoC is 2,048 KB or 2 MB of L1 Cache


                    In addition to the L1 Cache total, all 4 of the High Performance Core share 12 MB of L2 cache. Each of the 4 Low Power Cores share a separate 4 MB of L2 Cache. Total L2 Cache on die in each M1 SoC is 16 MB.

                    I have not confirmed this but there are some reports that Apple partitions 16 MB of its on board storage as L3 Cache.


                    https://en.wikipedia.org/wiki/Apple_M1
                    Last edited by Jumbotron; 20 November 2020, 09:37 PM.

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                    • Originally posted by BillBroadley View Post

                      AMD is 32KB L1, Intel is 48KB. A 64KB-128KB datastructure that was used heavily would HEAVILY favor the M1.

                      See my above post to evergreen. The M1 is chock a block full of cache. More so than any other CPU either Intel, AMD, Nvidia or ARM with the possible exception of IBM's upcoming POWER 10 CPU. And that ain't showing up in any laptop anytime soon.

                      As a matter of fact, the sheer amount of Cache in each and every M1 is historical. There has never been a consumer chip with as much cache. On top of that it is the ONLY CPU in consumer tech history to also have low latency High Bandwidth Memory directly attached to each core with a zero memory copy, cache coherent interconnect. Also, with the exception of the POWER 10, the M1 may be the ONLY SoC in the world with this architecture.

                      The memory parallelization in the M1 is simply beastly and an engineering marvel. Where AMD and ARM pioneered Heterogeneous System Architecture and until the abandonment of HSA by AMD of the FUSION line of APU's to pursue ZEN, Apple seems to have picked up that mantle and perfected it and did it in a package with a 13.8 watt max thermal profile.
                      Last edited by Jumbotron; 20 November 2020, 09:38 PM.

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