Originally posted by AdrianBc
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Originally posted by AdrianBc
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- The length of the critical path of a pipeline stage. In a simplified view: max frequency = the speed of light divided by the length of the critical path; the speed of light is a constant.
- An increase in frequency requires an increase in current and/or voltage for the CPU to operate correctly at the higher frequency. This generates additional heat that does not contribute to computation and has to be moved away from the CPU die before it will result in a hardware error.
- More pipeline stages enable a shorter critical path (because the CPU's work is being subdivided into smaller units)
- Excessive focus on shortening the critical path results in a lower IPC (instructions per clock) of the CPU (Pentium 4)
Skylake and Sunny Cove have the same number of pipeline stages: 14-19.
The length of the critical path depends on the number of transistors used to perform a particular function. Sunny Cove increases the size of the L1D cache to 48 KiB (Skylake: 32 KiB). Sunny Cove L1D latency increases to 5 cycles (Skylake: 4-6 cycles).
It is possible, although unlikely, that Sunny Cove with a much larger CPU core than Skylake has a critical path of the same length as Skylake (because of more advanced (better tuned) algorithms in Sunny Cove).
https://en.wikichip.org/wiki/intel/m...kylake_(client)
https://en.wikichip.org/wiki/intel/m...res/sunny_cove
https://software.intel.com/content/w...ce-manual.html
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