No announcement yet.

A Kernel Maintainer's Prediction On The CPU Architecture Landscape For 2030

  • Filter
  • Time
  • Show
Clear All
new posts

  • #21
    Originally posted by Weasel View Post
    He's either a clown, or trolling.
    He's talking about the 128-bit CHERI RISC-V ISA (CHERI = Capability Hardware Enhanced RISC Instructions), which uses the extra bits for capabilities. They are not doing this to simply further increase the virtual address space.

    From their FAQ:

    we explored and developed a 128-bit compressed capability format employing fat-pointer compression techniques. This approach exploits redundancy between the two 64-bit virtual addresses representing bounds and the 64-bit pointer itself. The CHERI-128 approach retains strong C-language compatibility (e.g., out-of-bounds pointers) and retains our required security properties (e.g., monotonicity), while also achieving good microarchitectural performance (i.e., avoiding multi-cycle delays for key operations). 128-bit capabilities substantially reduce the data-cache overhead of CHERI for pointer-intensive workloads. Support for 128-bit capabilities can be found in recent versions of our CHERI FPGA prototype and also QEMU-CHERI. Our 2019 IEEE TC paper on CHERI Concentrate documents our approach in detail.


    • #22
      Originally posted by c117152 View Post
      More importantly, as the x86 patents dry out there will be new x86 players
      No. Intel and AMD take care of generating enough new patents to make using the old patent free parts pointless.


      • #23
        Originally posted by skeevy420 View Post
        One thing I don't think was considered is all the lost trust in x86, because, let's face it, for desktop users the only thing x86 has going for it anymore is that it plays games better than the rest.
        x86 is also more generic in terms of booting and standards. This ARM SoC device tree thing is a PITA.


        • #24
          Originally posted by pal666 View Post
          you have plenty of room to grow in third dimension
          Heat dissipation will be glad to hear that..


          • #25
            Originally posted by danmcgrew View Post
            I would, honestly and objectively, like you to expand on what you perceive the technical reasons for your statement to be, and definitely not for the purposes of starting an argument.

            For a long time, I have been involved in the 'word-length-growth' of processors at a more technical level than most, starting with Intel's '4004 / 4040' and Japanese 4-bit CPUs, to where we are now.
            The address space is just too big. But humans have a problem understanding just how big some numbers are. You can address enough bytes to almost cover all the grains of sand on the planet.

            But that's not the only problem. The thing is that memory is useless if you don't make use for it. RAM is supposed to be fast memory, it's not for long-term storage. Right?

            And remember that in practice, you will almost never use full memory bandwidth, since most stuff will require calculations (that's what the CPU is for after all). But nevertheless, how fast do you think you can read the memory?

            Even if you read the memory at 4 TB / sec, which is insanely fast, it would take you 4194304 seconds to read all of it just once. This doesn't even include writing it. That's 48 days.

            Of course, physical address space is different than virtual, but the numbers are insane either way (not to mention you can have multiple processes).

            And that's just 64-bit... 128-bit can possibly address one byte for each atom on Earth.

            Want to know about 256-bit? Enough addresses for all the atoms in the entire observable Universe.


            • #26
              Originally posted by sebastianlacuesta View Post
              Sure, 640 kB ought to be enough for anybody.

              Math ain't your forte I guess.


              • #27
                There's a lot of research being done into using light/photons instead of electricity/electrons in processors. Who knows if it'll be able to overcome the limitations of physics that exist with electricity and silicon.


                • #28
                  Originally posted by s_j_newbury View Post
                  I expect we'll be in an economic depression for the next decade at least
                  I disagree, I truly believe that as soon as a viable vaccine hits the market, you will see the economy skyrocket; I believe this so much I put everything I can into the stock market, buy as many shares of airlines, movie theaters and pharmaceutical companies as I could afford, and I also bought a bunch of Uber stock. I work for a very large medical company, we are big enough that when Mr. Trump invited CEO's from various medical firms to meet him in the White House, my company's CEO was there.

                  All projections within the industry are that a viable vaccine is nearly here, with the first vaccinations predicted to begin before the year is out and mass vaccination by mid 2021.

                  I think you are about to see a Supply Crunch, as vaccinations role out, people are going to want to go out and spend money and the Demand is going to far exceed the Supply. The current economic downturn is not an "organic" one, it didn't happen due to market forces, it happened due to legislative actions taken world-wide to try and combat a pandemic, once those restrictions are lifted the economy is going to grow and you will probably see a Labor Crunch, a shortage of people available to fill even non-skilled positions as Demand outpaces Supply.

                  But overall, I think you'll see an economic expansion similar to what happened after WW2.


                  • #29
                    Most pf this guy's predictions fall into the category of "no shit, Sherlock".


                    • #30
                      Originally posted by Space Heater View Post

                      He's talking about the 128-bit CHERI RISC-V ISA (CHERI = Capability Hardware Enhanced RISC Instructions), which uses the extra bits for capabilities. They are not doing this to simply further increase the virtual address space.

                      From their FAQ:

                      University of Cambridge Technical Report number 927--
                      "CHERI RISC-V ISA"

                      What a pile of unmitigated horse-shit.

                      If the 496-page document (yes; you read that correctly--FOuR HUNDRED and NINETY-SIX PAGES) referenced in THIS pile of shit is not enough (wherein is mentioned not only a 128-bit architecture, but a 256-bit architecture), just wait--

                      "... we are actively improving the specification and anticipate an updated version in the forthcoming CHERI ISAv8 (due 2020Q2)...”
                      ************************************************** *************************************
                      Ever occur to you that all this verbiage and monumental effort centers around a RISC machine? That stands for "Reduced Instruction Set Computer", people.
                      Apparently THEY have not.

                      If you'd like to know who "they" are--besides generating 500-page 'Research Reports", their modesty extends to including photographS of the entire 'research team'.

                      Someone(s) has found a way to a guaranteed source of income.
                      Last edited by danmcgrew; 01 September 2020, 02:25 PM.