Latest Linux Patch Further Confirms Intel Alder Lake As A Hybrid Core Design

[phoronix]

Phoronix: Latest Linux Patch Further Confirms Intel Alder Lake As A Hybrid Core Design

Jiving with all the recent rumors, the latest Linux kernel patch work further spells out clearly that Intel Alder Lake will feature a hybrid core design akin to Arm's big.LITTLE architecture...

http://www.phoronix.com/scan.php?page=news_item&px=Intel-Alder-Lake-Hybrid-Model

[brunosalezze]

Intelsure looks like a sinking ship, with these many leaks.
Rocket lake is not even announced yet and everybody knows that is a 14nm backport 8-core Sunny/Willow cove design.
And these many leaks are for the next socket 1700.

[ssokolow]

Intelsure looks like a sinking ship, with these many leaks.
Rocket lake is not even announced yet and everybody knows that is a 14nm backport 8-core Sunny/Willow cove design.
And these many leaks are for the next socket 1700.

Don't count them out too soon. Last I checked, they had a ton of cash on hand, and AMD was an order of magnitude smaller, meaning that supply issues may force big companies to go Intel. (I remember that being why Dell was offering only Intel at one point. They didn't want to further subdivide their product lines and AMD couldn't guarantee sufficient supply to outfit all units in a specific model.)

Intel's got plenty of time to turn things around if they get their heads out of their asses.

[brunosalezze]

Don't count them out too soon. Last I checked, they had a ton of cash on hand, and AMD was an order of magnitude smaller, meaning that supply issues may force big companies to go Intel. (I remember that being why Dell was offering only Intel at one point. They didn't want to further subdivide their product lines and AMD couldn't guarantee sufficient supply to outfit all units in a specific model.)

Intel's got plenty of time to turn things around if they get their heads out of their asses.

You got it wrong pal. A sinking ship has many leaks, I never mentioned anything in terms of financial bankruptcy, they are doing very well, I know.

[milkylainen]

I absolutely hate asymmetric compute units like this. Not only does the scheduler need to be aware,
but latency, frequencyscaling, voltagescaling, instruction support etc. Everything needs to be aware.
It's just a piping hot mess. I prefer symmetric fast cores that return to an idle state faster vs more asymmetry and longer execution times.

I get the point, but it's just plain ugly in my eyes.

[starshipeleven]

Intelsure looks like a sinking ship, with these many leaks.
Rocket lake is not even announced yet and everybody knows that is a 14nm backport 8-core Sunny/Willow cove design.
And these many leaks are for the next socket 1700.

you mean 14nm++++++++++++++++++++++++++++++++++++++++++++++ ++++
right?

[starshipeleven]

I absolutely hate asymmetric compute units like this. Not only does the scheduler need to be aware,
but latency, frequencyscaling, voltagescaling, instruction support etc. Everything needs to be aware.
It's just a piping hot mess. I prefer symmetric fast cores that return to an idle state faster vs more asymmetry and longer execution times.

I get the point, but it's just plain ugly in my eyes.

I'm guessing Intel will come out with something like:

"Don't worry, if all of that is hard, let the friendly neighborhood Management Engine take care of that for you."

[M@GOid]

The fact they are resorting to Atom cores to help with power eficiency, makes me think their problems with the 10nm are worse than I thought.

Or this can be a game changing for x86 architecture in portable devices. Who knows.

[discordian]

I absolutely hate asymmetric compute units like this. Not only does the scheduler need to be aware,
but latency, frequencyscaling, voltagescaling, instruction support etc. Everything needs to be aware.
It's just a piping hot mess. I prefer symmetric fast cores that return to an idle state faster vs more asymmetry and longer execution times.

You know how much time it takes to enter/exit an deeper idle state, and scaling frequency and/or voltage? There are 8 C-States and 2 P-States (possible more now, not up-to date on this), and the times vary on other things like frequency aswell.

Using different cores is not really more complicated that handling freq-scaling and a dozen low power states (and predicting their effects on powerdraw and performance).
Of course doing both ain't helping things

I get the point, but it's just plain ugly in my eyes.

Do you actually have to deal with any of the problems or is this some "philosophically anger" ?

[discordian]

Kinda weird, as current Atoms don't have AVX, and i'd guess that future Atoms wont either.