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JEDEC Publishes DDR5 Standard - Launching At 4.8 Gbps, Better Power Efficiency
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Originally posted by blueweb View PostAPU this, APU that. Just a reminder that APU = AMD marketing for CPUs with an iGPU.
Practically all Intel CPUs are "APUs" since nearly forever. They don't seem to be an endangered species.
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Originally posted by TemplarGR View Post
Source? This is the first time i read something like this. If AMD APUs actually had 256MB of cache, they would have had much better performance in gaming than they do. Unless you refer to specific laptop models or something, but still, this is news to me.
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TemplarGR Ok, thanks for the details. I was sure the architecture would be different. It is not clear to me if APU actually implies a certain architecture instead of just the notion of CPU + GPU in the same package. And besides, the actual APUs, regardless of original vision, are not homogeneous, but still Zen + Vega, so isn't this just semantics?
Last edited by tildearrow; 15 July 2020, 10:43 PM.
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Originally posted by Brane215 View Post
I hope they won't rush it. NO need DDR4 started at pathetic 2133 speeds and was nothing to write about until 3600MHz+ speeds.
Aiming it for APUs is fruitless, at least on start. WHole point of APU solution is low price. Which kinda evaporates if you have to have expensive fast RAM.
Once market stabiilizes and 6000MHz speeds become normal, sure. By then you'll probably get 64GB per stick and ECC will be off-the-shelf normal...
BTW, there is far too big of a crowd of me-too morons o'n the board market. All generic copies, with the exception of a bord or two from Asrock and perhap Biostar etc, everything is generic.
I would love to see cheap SoC board with say soldered on 4800HS and soldered on LPDDR4 at 4266MHz quad channel.
ANd the same with a successor on LPDDR5. With all four DP ports on small , cheap but deadly mini-ITX or smaller board, without chipsed. Basically just with that the APU offers.
But no, we are to be forcefeed bazziliion same models with different name.
While I'm a little down on Apple when it comes to PC's at the moment; I'm really looking forward to seeing what the shipping Apple Silicon is all about. Anything legacy will likely be abolished on the new machines. Say what you will about Apple but they have the balls to drop old tech far sooner than the PC world every does. We still have PC oriented motherboards shipping with old style keyboard and mouse sockets, which just blows the mind.
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Originally posted by Brane215 View PostAiming it for APUs is fruitless, at least on start. WHole point of APU solution is low price. Which kinda evaporates if you have to have expensive fast RAM.
Once market stabiilizes and 6000MHz speeds become normal, sure. By then you'll probably get 64GB per stick and ECC will be off-the-shelf normal...Last edited by MrMorden; 14 July 2020, 10:26 PM. Reason: You get a comma! You get a comma! EVERYONE GETS A COMMA!
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Originally posted by ThoreauHD View PostAM5/Pcie5/ddr5 will be my next upgrade stop I think. We're approaching the point where the slowest part of the boot process is the bios loading.
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Originally posted by ms178 View Post
The notion that APUs are destined for the low-cost segment (with all of the constraints that implies) doesn't need to be true in the future anymore.
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Originally posted by wizard69 View PostWith the move to SSD's and multi core low wattage chips, a Small Form Factor machine today will beat the pants off a 5 year old desktop tower machine.
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Originally posted by sdack View PostIt is spelled HBM - High Bandwidth Memory.
Originally posted by sdack View PostHBM is generally a lot faster than DDR. They are basically the same memory, but HBM was designed as a stack of memory chips so one can have a very wide bus and get past the bottleneck. And we need HBM not only for GPUs, but for CPUs when we want to increase the core count. A picture says it all:
So much of a die in an AMD EPYC gets wasted on cache just to keep it fed, the design gets bend over to fit the needs of caches, software needs to be adjusted to take it into account, and the moment every core wants to access main memory the whole performance still goes to shit. All because DDR cannot keep up.
I agree that HBM2 provides more margin for even higher data rates and is a technically elegant solution.
HBM2 is a traditional trade:
Low pin count, higher frequency (high power), lower cost (DDR). For higher pin-count, lower frequency (low power) and high cost (HBM2).
Bandwidth is pretty similar within the same cost, as is latency.
The problem with HBM is that it's pincount is one magnitude higher. Hence need for an interposer and a local structure (preferrably).
It'll work fine for high end GPUs but HBM2 is going to be difficult for very large memory sizes with CPUs.
I don't know how you would suggest a modular x86 memory architecture for 64G+ RAM sizes?
The interposer structure would be extremely cumbersome. Cost would go through the roof.
I'm pretty sure it can be done, and cost will eventually drop.
But I don't think it will ever catch plain PCB-mounting DDRs in that aspect.
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