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JEDEC Publishes DDR5 Standard - Launching At 4.8 Gbps, Better Power Efficiency

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  • #11
    Originally posted by Brane215 View Post

    I hope they won't rush it. NO need DDR4 started at pathetic 2133 speeds and was nothing to write about until 3600MHz+ speeds.

    Aiming it for APUs is fruitless, at least on start. WHole point of APU solution is low price. Which kinda evaporates if you have to have expensive fast RAM.
    The notion that APUs are destined for the low-cost segment (with all of the constraints that implies) doesn't need to be true in the future anymore.

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    • #12
      Originally posted by ms178 View Post

      The notion that APUs are destined for the low-cost segment (with all of the constraints that implies) doesn't need to be true in the future anymore.
      In that future, those APU will either have HBM3 and/or gigantic cache, so they won't depend on fast RAM so much.
      And even if you plop it on those, no one will care about extra $100 or $200.

      BUt for cheap ones you'll want affordable RAM at good speeds.

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      • #13
        Originally posted by skeevy420 View Post
        AMD's APUs will love this.
        Yes, but APU is a dead concept unless AMD puts some L4 cache on them. Transistors shrink faster than memory bandwidth improvements, to the point where AMD stopped really improving the CUs on their APUs because memory is a huge bottleneck and they get wasted anyway.

        They need to add L4, unified for both cpu and igpu. It doesn't need to be a lot of cache, even 256MB-512MB could be HUGE for gaming and gpgpu (remember in around 2014 Intel's 128MB eDRAM cache? ). And at 7nm+, i don't think it is that hard or costly. Then add some more CUs on those APUs, and voila, you have a proper 1080p gaming APU able to play quite well all next gen games. It will sell like hotcakes and what's better, it will spread AMD's HSA around and create an established hardware base for it.

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        • #14
          Originally posted by skeevy420 View Post
          AMD's APUs will love this.
          A non local memory bus does not provide near enough bandwidth or low latency in comparison.
          A modern HBM2 or GDDR5x stack provides a GPU with something like ~1TB/sec of bw.
          Of course a highly optimized and wider memory bus. But still.
          Last edited by milkylainen; 07-15-2020, 02:41 AM. Reason: Correct HMB typo.

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          • #15
            Originally posted by Brane215 View Post
            no one will care about extra $100 or $200.
            Really? Why do you think HBM isn't being used on APU's right now?

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            • #16
              People, ram price goes down half when the next model is out, example:
              GDDR6 = 11$ per GB
              GDDR5 = 5.5$ per GB
              HBM2 = 11$ per GB + 25$ interposer
              HBM1 = 5.5$ per GB + 25$ interposer
              Also Intel Apus do have 64-256MB EDcache, they don't depend on DDR4 that much.
              Last edited by artivision; 07-14-2020, 08:23 PM.

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              • #17
                Originally posted by templargr View Post

                yes, but apu is a dead concept unless amd puts some l4 cache on them. Transistors shrink faster than memory bandwidth improvements, to the point where amd stopped really improving the cus on their apus because memory is a huge bottleneck and they get wasted anyway.

                They need to add l4, unified for both cpu and igpu. It doesn't need to be a lot of cache, even 256mb-512mb could be huge for gaming and gpgpu (remember in around 2014 intel's 128mb edram cache? ). And at 7nm+, i don't think it is that hard or costly. Then add some more cus on those apus, and voila, you have a proper 1080p gaming apu able to play quite well all next gen games. It will sell like hotcakes and what's better, it will spread amd's hsa around and create an established hardware base for it.
                tl;dr: HBM2

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                • #18
                  Originally posted by DanL View Post

                  Really? Why do you think HBM isn't being used on APU's right now?
                  because it isn't on any that means anything on the market right now.
                  Collection items excluded.

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                  • #19
                    Originally posted by milkylainen View Post
                    A non local memory bus does not provide near enough bandwidth or low latency in comparison.
                    A modern HMB2 or GDDR5x stack provides a GPU with something like ~1TB/sec of bw.
                    Of course a highly optimized and wider memory bus. But still.
                    It is spelled HBM - High Bandwidth Memory.

                    HBM is generally a lot faster than DDR. They are basically the same memory, but HBM was designed as a stack of memory chips so one can have a very wide bus and get past the bottleneck. And we need HBM not only for GPUs, but for CPUs when we want to increase the core count. A picture says it all:



                    So much of a die in an AMD EPYC gets wasted on cache just to keep it fed, the design gets bend over to fit the needs of caches, software needs to be adjusted to take it into account, and the moment every core wants to access main memory the whole performance still goes to shit. All because DDR cannot keep up.

                    If one has got the choice between a graphics card with GDDR5X and HBM2 then one should go for HBM2, because the sooner DDR dies the better and the more HBM gets bought the faster its price will drop.

                    AMD has a video on it, which explains a bit more. The guy claims AMD would have invented it, but I think it might just be a figure of speech where he simply identifies with the development. As far as I know was it Hynix. Not that it's all that import. Seeing AMD getting behind it matters more:


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                    • #20
                      APU this, APU that. Just a reminder that APU = AMD marketing for CPUs with an iGPU.

                      Practically all Intel CPUs are "APUs" since nearly forever. They don't seem to be an endangered species.

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