Intel Details Lakefield With Hybrid Technology

[AdrianBc]

I don't understand one thing. How they going to deal with ISA differences? Tremont cores most likely won't support AVX "class" instructions for example (and perhaps several more). Say application has AVX compiled-in, will OS scheduler know this somehow and choose core accordingly? Will developers have to support this explicitly in applications? How ARM deals with it? (well I guess they use one ISA per family) Could someone explain this to me, thanks.

They have chosen the easy way, so they have disabled AVX, AVX2, FMA & AVX-512 on the Ice Lake Core and presumably also the other ISA extensions available since Haswell or Broadwell (BMI1, BMI2, ABM, ADX).

Therefore all 5 cores can execute only the ISA provided by Tremont, with only 128-bit SSE SIMD.

[ldesnogu]

They have chosen the easy way, so they have disabled AVX, AVX2, FMA & AVX-512 on the Ice Lake Core and presumably also the other ISA extensions available since Haswell or Broadwell (BMI1, BMI2, ABM, ADX).

That's exactly what we need: more castrated cores stuck to an ISA announced in 2008.

[starshipeleven]

Uhh, not to spoil things, but it sounds like you never watched the later parts of the show. And large portions of it are far more interested in human vs human conflict than the machines.

[spoiler alert]
Yeah, it's not like half the VIP characters are secretly hybrids (so secretly that they don't even know it themselves, which is puzzling) and every time a evil cylon hybrid talks in the screen time dedicated to evil hybrids doing evil things on their own ships and planets it's always talking about insane religious bullshit and and allusions for days.
[spoiler alert]

[AmericanLocomotive]

I don't understand one thing. How they going to deal with ISA differences? Tremont cores most likely won't support AVX "class" instructions for example (and perhaps several more). Say application has AVX compiled-in, will OS scheduler know this somehow and choose core accordingly? Will developers have to support this explicitly in applications? How ARM deals with it? (well I guess they use one ISA per family) Could someone explain this to me, thanks.

It actually has been a problem on some phones. There's a certain Samsung big.LITTLE SoC where the big and little cores did not share quite the same ISA. The little cores were actually "ahead" and supported more instructions. The SoC reported the availability of those instructions to the OS, but as soon as the OS moved the application over to the big core, it'd crash. Samsung later "fixed" it by just completely disabling those instructions on that phone.

I'm really curious to see how the OS schedulers are going to handle this on x86. Obviously they've worked it out pretty well on Android, but I don't think the x86 space has ever really had anything like this before. I'm also curious to see how highly-threaded applications deal with one core being significantly faster than the others.

They have chosen the easy way, so they have disabled AVX, AVX2, FMA & AVX-512 on the Ice Lake Core and presumably also the other ISA extensions available since Haswell or Broadwell (BMI1, BMI2, ABM, ADX).

Therefore all 5 cores can execute only the ISA provided by Tremont, with only 128-bit SSE SIMD.

Yikes. Seems like a great way to slow the adoption of new instructions by introducing a mainstream product that doesn't even support instructions that are ~10 years old.

[DavidC1]

Intel lied on the TDP, so all the parts that were supposed to go into smartphones either had issues when put into smartphones or didn't sell, Intel tried to pivot into tablets and mini-PCs, but apart from a few select models that had half-decent internal storage, most devices got the lower ends of eMMC and Windows really ran like garbage on that.

What? After Medfield it was competitive in the battery life/thermals front. Being on Windows is also the reason why Windows RT's deaths were accelerated. Without it, it would have had reasons to exist even with all the faults. I had an 8-inch Bay Trail device. Pre-Bay Trail was dog slow, but BT was very useful. Of course you still had the issue of Windows 8/8.1 having a subpar Tablet UI, but it was compact and got 7-8 hours(despite the tiny 15WHr battery).

The real issue on Android is that major vendors had their own SoCs and not only had to go against that, but Android apps had to be emulated due to being x86. I read user reviews too. The complaint was random incompatibilities and slow downs.

[jayN]

The story behind Lakefield was that it was specified by Microsoft. Maybe Windows 10x will come next year and we'll see it in a Neo. Microsoft required the low standby power, which Intel solved by using the low leakage 22FFL process on the io layer. I see Intel reporting it can be as low as 2.5mW. They show a different io layer process in the roadmap for the next generation.

[aht0]

For the kids watching from home:
This is an image of a Cylon Hybrid (human-looking machine of evil machine empire) from the Battlestar Galactica universe.
I had to ask Google image search about wtf is this from, I've never been a fan of BG myself.

EDIT: now more generic

I belive that particular individual acted as an sort of "plug-in" AI for one of the big mothership/carriers, being permanently affixed into that "bath of light" and babbling most of the time incoherently about something they experienced. It was quite watchable series for it's time, haven't seen anything from more recent years I'd watch with such interest anyway.