Announcement

Collapse
No announcement yet.

Arm Announces Cortex-A78, Cortex-X Custom

Collapse
X
 
  • Filter
  • Time
  • Show
Clear All
new posts

  • #11
    Originally posted by Jabberwocky View Post
    I still don't trust banking, insurance and some communication applications and I can't be a responsible/productive member of modern society without those. I use my mobile device for two factor authentication, so from a professional and ethical perspective it's extremely important for my device to be secure from top to bottom.
    Security is important in the mobile space. However, like on your PC, by far your biggest risk is not from a Spectre-style attack but from downloading an app with a virus or clicking on a link a "friend" sent. If you avoid that, there is generally little to worry about. A long time ago, I connected my brand new Windows PC to the internet and got infected with a worm within 5 minutes due to the total lack of security at the time. Things changed.

    Comment


    • #12
      Originally posted by discordian View Post
      Well, then why have multiple layers of caches? Just put everything in L1.

      Its a balance of size/speed (bigger cache = slower access) and power(-efficiency), and the sum is that the chip is now balanced differently and in sum is faster than its predecessor.
      I'm just mentioning the PR rationale behind these moves. I mean whatever they do, they always tout it as an improvement. Whether the cache goes up or down, well... you guessed it: It's always an improvement

      Comment


      • #13
        Originally posted by PerformanceExpert View Post
        Security is important in the mobile space. However, like on your PC, by far your biggest risk is not from a Spectre-style attack but from downloading an app with a virus or clicking on a link a "friend" sent. If you avoid that, there is generally little to worry about. A long time ago, I connected my brand new Windows PC to the internet and got infected with a worm within 5 minutes due to the total lack of security at the time. Things changed.
        This, plus the actual volume of mobile malware in the wild is very low. I have Android phones from ~2014 that I've *tried* to infect with Android malware and was unsuccessful. Side channel attacks like Spectre are more the territory of nation state actors (and it's a large effort, even for them), pretty far removed from the petty crooks and organized crime who want to pilfer your wallet. It's not worth losing any sleep over.

        Agreed 100% that it's your personal behavior (clicking malicious links, loading malicious apps, etc.) that is by far the biggest threat to mobile device security. Use common sense, and you'll be fine.
        Last edited by torsionbar28; 26 May 2020, 02:36 PM.

        Comment


        • #14
          Originally posted by _Alex_ View Post
          Since when is halving the L1 cache size an ..."improvement"?

          I guess when cpu manufacturers raise it they claim it's a performance improvement and when they reduce it they claim it's an efficiency improvement... They can never lose
          Since L1 cache is the fastest memory in the system (save for registers), it's also the most power hungry.
          And yes, efficiency is at odds with performance. When one wins, the other one loses.

          Comment


          • #15
            Umm... The Cortex-series are not SoCs, but CPU cores sold as IP cores (i.e designs ready-fort-synthesis laid out in Verilog/VHDL) to various companies who make SoCs. To call them as such is like calling a Yamaha engine a "car" when they're just component parts that Yamaha makes based on design specs given to them by carmakers like Volvo and Toyota.

            I see they're just going bigger and bigger with these cores in terms of transistors per core. Some size growth is completely natural, but it feels like ARM is now very much aiming at continually growing the cores until they have a real desktop replacement in their hands. All the while my current phone uses four comparatively tiny A53 cores and I don't think I need anything considerably faster.
            "Why should I want to make anything up? Life's bad enough as it is without wanting to invent any more of it."

            Comment


            • #16
              Originally posted by bug77 View Post

              Since L1 cache is the fastest memory in the system (save for registers), it's also the most power hungry.
              And yes, efficiency is at odds with performance. When one wins, the other one loses.
              It's never either/or. Like with software, hardware is not 100% optimal, so there is always plenty room for improvement of every aspect. You can improve performance and get better efficiency. For example, replace the branch predictor with a larger one that uses the same amount of power. Your performance improves due to fewer branch mispredictions, and as a result your efficiency improves. Similarly improve efficiency and as a result performance improves in power constrained scenarios.

              Comment


              • #17
                Originally posted by L_A_G View Post
                I see they're just going bigger and bigger with these cores in terms of transistors per core. Some size growth is completely natural, but it feels like ARM is now very much aiming at continually growing the cores until they have a real desktop replacement in their hands.
                Absolutely, the X1 will be pretty much equivalent in performance to 3950X according to AnandTech. That would allow seriously fast laptops and desktops!

                Comment


                • #18
                  Originally posted by L_A_G View Post
                  I see they're just going bigger and bigger with these cores in terms of transistors per core. Some size growth is completely natural, but it feels like ARM is now very much aiming at continually growing the cores until they have a real desktop replacement in their hands.
                  ARM now has both efficiency (A78) and performance (X1) flagships. The transistor count increases, but the overall size decreases (for A78 compared to A77 by 15%) while still improving performance because of the 5nm manufacturing process.

                  Originally posted by PerformanceExpert View Post
                  Absolutely, the X1 will be pretty much equivalent in performance to 3950X according to AnandTech. That would allow seriously fast laptops and desktops!
                  I'd be very sceptical about a performance projection based on PR materials. When X1 comes out in a real product it might have to compete with whatever is after Tiger Lake for Intel, AMD Zen 3 and the next Apple core. Architectural reveals are always exciting, but it takes a while for real benchmarks of the final products

                  Comment


                  • #19
                    Originally posted by PerformanceExpert View Post

                    It's never either/or. Like with software, hardware is not 100% optimal, so there is always plenty room for improvement of every aspect. You can improve performance and get better efficiency. For example, replace the branch predictor with a larger one that uses the same amount of power. Your performance improves due to fewer branch mispredictions, and as a result your efficiency improves. Similarly improve efficiency and as a result performance improves in power constrained scenarios.
                    Flawed example. You can only replace the branch predictor with a larger one that uses the same amount of power if you give up die space. So it's still either/or.
                    Or you can do it by using a smaller node, but then you're giving up using the same predictor and saving up die space. Still either/or.

                    The only case where you'd win across the board is if you redesign the branch predictor to be more efficient using the same number of transistors and die space (or less). And that happens, too. Just not so often as juggling other, known variables.

                    Comment


                    • #20
                      Originally posted by bug77 View Post

                      Flawed example. You can only replace the branch predictor with a larger one that uses the same amount of power if you give up die space. So it's still either/or.
                      Or you can do it by using a smaller node, but then you're giving up using the same predictor and saving up die space. Still either/or.
                      No, it's not either/or. A predictor might use more area and can still be more efficient. If say it required 5% more area but performance improves by 6%, the perf/area efficiency is better.

                      The only case where you'd win across the board is if you redesign the branch predictor to be more efficient using the same number of transistors and die space (or less). And that happens, too. Just not so often as juggling other, known variables.
                      No, you don't need the same power or number of transistors to improve efficiency. All you need to do is improve performance by more than the area or power cost. As an example imagine halving the L1 cache in Cortex-A78 giving 2% lower performance, reduce area by 3% and power by 2%. That would be an improvement in perf/area and neutral in perf/Watt. You might be able to make up for the performance loss elsewhere since you can now add 2% extra power. CPU designers make many of these kinds of tradeoffs.

                      Comment

                      Working...
                      X