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It's About Time: MIPS Release 5 + Warrior P5600 Support Coming With Linux 5.8

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  • It's About Time: MIPS Release 5 + Warrior P5600 Support Coming With Linux 5.8

    Phoronix: It's About Time: MIPS Release 5 + Warrior P5600 Support Coming With Linux 5.8

    While MIPS Release 6 is the latest version of the MIPS ISA, the MIPS Release 5 support is finally set to be mainlined with the upcoming Linux 5.8 kernel cycle...

    http://www.phoronix.com/scan.php?pag...se-5-Linux-5.8

  • #2
    I keep waiting for MIPS to do something, anything, to put them back in the running. It seems they're just happy making tcp offload engines and tiny routers.

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    • #3
      Linux has supported the P5600 for 6 years now. It was originally enabled by this commit which built atop many preparatory changes before it: https://git.kernel.org/pub/scm/linux...b5a5c2b0bf53ee

      The new change for 5.8 is about building a kernel that *only* supports MIPSr5 instead of MIPSr2-MIPSr5. Notice that although the commit message describes many features from r5 the change doesn't add support for them - it's already there.

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      • #4
        Wave Computing (current MIPS owner) filed for chapter 11 bankruptcy protection a few weeks ago. It might be the final chapter for MIPS - a shame since it was one of the first RISC ISAs.

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        • #5
          Originally posted by squash View Post
          I keep waiting for MIPS to do something, anything, to put them back in the running. It seems they're just happy making tcp offload engines and tiny routers.
          I don0t think they are happy.

          afaik they are on their way out of that market as well, at least for Linux-based firmware. Most networking stuff is now some form of ARM, and there are some PowerPC in the high end network appliances too

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          • #6
            Originally posted by paulburton View Post
            Linux has supported the P5600 for 6 years now. It was originally enabled by this commit which built atop many preparatory changes before it: https://git.kernel.org/pub/scm/linux...b5a5c2b0bf53ee

            The new change for 5.8 is about building a kernel that *only* supports MIPSr5 instead of MIPSr2-MIPSr5. Notice that although the commit message describes many features from r5 the change doesn't add support for them - it's already there.
            I believe its not only that,
            P5600 has dedicated features that are not activated with mips32r5

            The only options you had before was:
            Code:
            #define MODULE_PROC_FAMILY "LOONGSON64 "
            #elif defined CONFIG_CPU_CAVIUM_OCTEON
            #define MODULE_PROC_FAMILY "OCTEON "
            With the new P5600 option you will activate, by default,
            Code:
            + select CPU_HAS_PREFETCH
            + select CPU_SUPPORTS_32BIT_KERNEL
            + select CPU_SUPPORTS_HIGHMEM
            + select CPU_SUPPORTS_MSA
            + select CPU_SUPPORTS_UNCACHED_ACCELERATED
            + select CPU_SUPPORTS_CPUFREQ
            + select CPU_MIPSR2_IRQ_VI
            + select CPU_MIPSR2_IRQ_EI
            + select HAVE_KVM
            + select MIPS_O32_FP64_SUPPORT
            https://git.kernel.org/pub/scm/linux...3196da23758092
            Last edited by tuxd3v; 05-24-2020, 12:42 AM. Reason: complement

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            • #7
              Originally posted by PerformanceExpert View Post
              Wave Computing (current MIPS owner) filed for chapter 11 bankruptcy protection a few weeks ago. It might be the final chapter for MIPS - a shame since it was one of the first RISC ISAs.
              I didn't knew about that..
              Its also weird, they brought mips and after they will fill bankruptcy?!

              What that means?
              Mips will become a US government ISA?

              Anyway, at least the Russians, will continue it..
              At the moment, the P5600, proved to be the fastest 32bits processor/Watt, at least in coremark..

              Comment


              • #8
                Originally posted by tuxd3v View Post
                I believe its not only that,
                P5600 has dedicated features that are not activated with mips32r5
                ...
                All of the options you list existed before, and could be enabled on MIPS32r2 kernels that worked just fine on P5600. Trust me, until I left MIPS/Wave ~3 months ago I was the maintainer of this code.

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                • #9
                  Originally posted by tuxd3v View Post
                  Its also weird, they brought mips and after they will fill bankruptcy?!

                  What that means?
                  How does bankruptcy work in Putin's Russia?
                  Here in the western world it means everything in the company is sold off to pay debts, or that some new big investor shows up and buys everything (and also the debt).

                  We don't know if "MIPS technologies" (the company that develops MIPS processors like "ARM holdings" company develops ARM processors) will still exist after this happens.

                  Mips will become a US government ISA?
                  Classic russian thing to say. Why would US gov need an ISA?

                  Anyway, at least the Russians, will continue it..
                  Not sure. The Baikal is using licensed MIPS cores. This means they did not design the MIPS CPU cores, they bought P5600 core design from "MIPS technologies" and integrated in their Baikal chip design (i.e. added memory controllers, sata, Pcie controllers, usb and so on). I don't think they are able to develop a new MIPS core on their own.

                  I mean, they can do it, but designing their own high-performance CPU cores requires much more money and people than just buying them from someone else.

                  That's why many companies use ARM architecture processors. They are just buying the CPU core design from "ARM holdings" instead of designing the core themselves.

                  The bankruptcy of the parent company of "MIPS technology" is a big risk MIPS architecture will be dead, as no more companies will be able to design MIPS cores without spending A LOT of money to do it.

                  Comment


                  • #10
                    Originally posted by paulburton View Post

                    All of the options you list existed before, and could be enabled on MIPS32r2 kernels that worked just fine on P5600. Trust me, until I left MIPS/Wave ~3 months ago I was the maintainer of this code.
                    I was left with the impression that some things were not activated like they should, or some features were not present for P5600, it doesn't even existed a probe for it..

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