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Linux 5.8 To See Support For POWER10's Prefixed Instructions

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  • Linux 5.8 To See Support For POWER10's Prefixed Instructions

    Phoronix: Linux 5.8 To See Support For POWER10's Prefixed Instructions

    Beyond the usual excitement of numerous x86 and Arm hardware advancements each cycle, Linux 5.8 is bringing new IBM POWER enablement work...

    http://www.phoronix.com/scan.php?pag...-Prefixed-Inst

  • #2
    Now I know what prefixed instructions are, how do they work and why would I use them -- they must offer some advantage but what?

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    • #3
      Why? Prefixing is a CISC concept but Power is RISC. Why!?

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      • #4
        Originally posted by cthart View Post
        Now I know what prefixed instructions are, how do they work and why would I use them -- they must offer some advantage but what?
        Might give you some visibility: https://ibm.ent.box.com/s/hhjfw0x0lr...fnbxh2fuo0fog0

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        • #5
          So... the prefix is to allow some instructions to take up a second 32-bit word for things like large relative jump addresses or immediate values. Less RISCy, but POWER(PC) have always been among the more 'complex' RISC CPUs. And it's increasingly necessary in a 64-bit world.

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          • #6
            Originally posted by marty1885 View Post
            Why? Prefixing is a CISC concept but Power is RISC. Why!?
            Because there's not enough opcode space left in the ISA for useful extensions. Here's an example of its use from the new version of the Power ISA document:
            Using new instruction prefix, added support for extended immediate displacements and PC-relativea ddressing for a specific set of GPR and VSR load and store operations.

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            • #7
              SPARC HPC-ACE and ARM SVE already do prefixed instructions for some cases, so it's not like this is going to cause the moon to explode. This gives PPC 34b immediates for some ops, which can be convenient; it also allows it to fit 5-operand and 6-operand forms of larger VSX instructions (with a common form being a distinct mask for the destination vector and both source vectors.)

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              • #8
                I may be wrong but I was under the impression that x86 and AMD64 and POWER were all CISC architecture instruction sets. ARM is a RISC chip design.

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                • #9
                  Originally posted by kylew77 View Post
                  I may be wrong but I was under the impression that x86 and AMD64 and POWER were all CISC architecture instruction sets. ARM is a RISC chip design.
                  To the extent that the terms mean anything, Power is and has always been RISC; it's from the second wave of 90's RISCs, alongside Alpha and to some degree PA. x86 and AMD64 are CISC. IBM also owns z/Architecture, which is CISC.

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                  • #10
                    IIUC, POWER9 suffers from some of the recent security holes (SPECTRE and similar). Will the POWER10 fix this ?

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