Weekend Discussion: How Concerned Are You If Your CPU Is Completely Open?

[azdaha]

so you think Bytecode Webassembly is only a technology for browser apps ?
at this point you are wrong. at the beginning of the development of this technology they started as web browser technology only yes
but thats "History" because today aim for this technology is the user-case outside of the browser.

in the end you will be able to develop any kind of app even server apps or databases by using bytecode webassembly technology.

thill will end the ISA war because it will run on any cpu who has a bytecode webassembly layer/engine.

Damn, I thought javascript was bad enough (Obviously skeptical, but, admittedly, entirely uninformed on webassembly stuff).

[azdaha]

even if you have what is termed an "open" CPU you still have both correctness to prove as well as layout and tapeout as opportunities for compromise. then, do you trust the *designers* when they say "oh yeees, we made a trustable chip, you can totally trust us on that" (yes there are companies that genuinely state this)

err no.

independent analysis. formal proofs that are also libre / open. this is how you get even remotely close to a trustable design. it is the approach we are taking with LibreSOC.

for tapeout, a different approach is needed, based on reputation. do you think that a Foundry would be happy to run a compromised design, knowingly or unknowingly? Foundry being a multi billion dollar business, that is. what would happen to them if they were caught? how long do you think they'd stay in business? what do you rate the probability of a Foundry allowing that to happen, even once?

Indeed; see the VIA Technologies arbitration in Hong Kong for an example of why companies (i.e. Foundry) want to avoid this. This also serves as an example of the proprietary designs being used methodically and deliberately for malicious intent.

[MaxToTheMax]

My Blackbird idled at 55W, where my Phenom 2 box idles at 50W. According to Guru3d, a 16-core Threadripper 1920x idles at 93W. Slightly apples and oranges, but I don't see how it's bad. For performance, arch optimizations have a great effect in lame/flac/etc, in compiling loads Powers usually beat the comparable 14nm x86 procs phoronix.

My 2950x idles just over 50 as well. If the Blackbird's idle power draw is better than I thought, then that's great news and I would be willing to stand corrected... but how many cores does yours have?

I have considered loading up a raptor with a POWER-to-x86 cross-compiler and using it as an ice cream node. Might be a fun project.

[coder]

I found the error: "Microsoft" and "Oracle"

do you really think that anything what comes from this evil companies has any useful purpose?

Java didn't come from Oracle, it came from Sun. Java existed for 15 years before Oracle bought Sun. And yes, Google thought it was useful enough to use as the basis for apps in Android. For quite a while, Java was popular for server-side development, as well.

I can't really say much about CLI, other than that it's open, standardized, and MS made it free to use in 2009.

Java is a high-level Bytecode instead webassembly is low-level-bytecode.

Please explain what makes Java Bytecode high-level and what makes Web Assembly low-level, by comparison. As I'm looking at them, they both seem pretty low-level to me.

this means java was designed to be as slow as possible and webassembly is deigned to have NATIVE speed(Like native ISA).

Nobody designs something to be "as slow as possible". Comments like this really damage your credibility.

[curaga]

I have an 8-core v1 POWER9 in there.

[MaxToTheMax]

OK, thanks. Until I know how to extrapolate up or down, I will refrain from making assumptions about how the higher-core-count models would do.

[curaga]

The Blackbird's power delivery can't handle the higher core count models at full clocks, they will throttle. If you want the bigger models, Talos 2 makes more sense.

[madscientist159]

OK, thanks. Until I know how to extrapolate up or down, I will refrain from making assumptions about how the higher-core-count models would do.

I can help there...from one of our 18 core test boxes at idle:

Chip 0 Nest:              +26.0°C  (lowest = +14.0°C, highest = +35.0°C)
Chip 0 VRM VDD:           +26.0°C  (lowest = +17.0°C, highest = +32.0°C)
Chip 0 :                  29.00 W  (lowest =  27.00 W, highest = 146.00 W)
Chip 0 Vdd:                3.00 W  (lowest =   2.00 W, highest = 120.00 W)
Chip 0 Vdn:                7.00 W  (lowest =   6.00 W, highest =   8.00 W)
Chip 0 Vdd:               +5.13 A  (lowest =  +2.63 A, highest = +133.00 A)
Chip 0 Vdn:              +10.25 A  (lowest =  +9.38 A, highest = +11.75 A)

revision        : 2.2 (pvr 004e 1202)

[MaxToTheMax]

I'm assuming you sum those power measurements. 39 watts ain't bad at all for an 18-core, even if that's just the CPU package itself. I will correct my original post.

EDIT: you don't sum them. It's just 29 watts for package power.

[madscientist159]

I'm assuming you sum those power measurements. 39 watts ain't bad at all for an 18-core, even if that's just the CPU package itself. I will correct my original post.

Actually, no -- the total package power is just the top line, the other two lines are specific subsystems inside the package that are known to use a lot of power (Vdd is roughly core power alone, for instance). In this example, the total power used by the CPU in idle is 29 watts, not 39 watts.

Incidentally, you can see from the same output that the package power peaks in the ~150W range for the workload this machine runs, which is pretty typical. If you do a purposeful burn stress test you'll see these peak into the 170-190W range for the package, though it takes some doing to get them that high.

On the other end of the spectrum I've taken the high end CPUs well past 240W through serious overclocking. Maybe not the best idea for longetivity, but compiles really fly that way...