AMD Announces EPYC 7532 + EPYC 7662 As Newest Rome Processors

[pegasus]

so I’m wondering why do you want fewer cores, it makes no sense to me.

Calculate the memory bandwidth required to feed a single avx2 unit 100% of the time. You'll discover that with avx2 heavy codes it makes no sense to have more cores than you can feed with data.
Another motivation is "per core" licensing model of highend engineering software. You pay 20k for a workstation and that's just a rounding error of a license cost ...

[wizard69]

Yes it is easier but it's kind of retarded to disable cores and sell the part for cheap when you could NOT disable the core and sell this CPU for A LOT more as a mid/high end part. AMD CPUs are literally flying off the shelves in server market at the moment, and that takes priority over cheaper parts.

The bigger issue is that disabling cores isn’t a huge impact on overall thermals. Disabling cores due to defects is another thing but AMD doesn’t seem to offer a lot of variants due to defective cores. It is probably easier for them to simply sell the defective chiplet as a consumer part than to muddy the Rome lineup. It would be very interesting to know what is actually happening but I get the feeling that yields are very good.

[MrEcho]

I would love to see a Ryzen with 1GB of L3/L4, they have enough room on the socket todo so. With this chiplet design, it opens up options.

[wizard69]

So they're still holding back on the lower core count cpus with full cache? Or maybe the niche for those cpus is just too small for them ... It's maybe easier to develop a bios feature to disable some number of cores per ccx.

There is no incentive to hold back. The cores in these processors are not as power hungry as some might imagine. Caches on the otherhand are very power hungry and as such are limited in size to keep power in check.

so I’m wondering why do you want fewer cores, it makes no sense to me.

[franglais125]

At this rate we'll express CPU cache in GB in a few years. Wouldn't that be nice. As others said already, that's bigger than early HDDs!

[wizard69]

And here I was thinking the original amount of cache was a lot...

I can remember dreaming about a desktop with 256mb of RAM as the next best thing. That makes me old but highlights just how far tech has come in a couple of decades.

[Marc Driftmeyer]

No kidding. This CPU cache is larger than my first hard drive. Woah!

You're young.

[starshipeleven]

(thats why modern chips have issues with radiation hardness for space equipment - very nice dense grid which can easily affected by some charged particle passing by...sry OT).

Ummmmmmm.... I think it was more that modern stuff is very miniaturized so charged particles have an easier time changing component state or punching holes, while affecting larger, heavier and dumber components requires more energy because they are simply bigger.

Older chips are actually very much larger in surface space (at the same relative performance), they are printed at 80nm or even bigger process nodes.

I mean, how many Pentium IV do you need to amass to actually get anywhere near the performance of a modern CPU? how much square meters of silicon surface is that lol?

My underlying question is if you can disable low performing /defective areas as easy as you can disable "core" unit or is it necessary to take the cache as a whole. For the sake of simplicity let us just talk about L3.

Yeah. Cache is usually designed as a modular bunch of smaller cells that can be disabled independently so you can minimize the amount of cache lost for every defect.

Otherwise having a single defect in the cache block would mean you have to disable the whole block so you end with some cores that have no attached L1/L2/L3 cache, that's insane, you are trashing that core's performance.

[CochainComplex]

Cache is a pretty big surface area (relatively speaking) so yeah, defect caches are a thing just as defect cores.

Yes this I have seen on multiple die shots. (thats why modern chips have issues with radiation hardness for space equipment - very nice dense grid which can easily affected by some charged particle passing by...sry OT).
My underlying question is if you can disable low performing /defective areas as easy as you can disable "core" unit or is it necessary to take the cache as a whole. For the sake of simplicity let us just talk about L3.

[skeevy420]

What a time to be a sysadmin. When single socket 32 core processors are the mid tier ...... . Not long ago i remember a sysadmin calling a dual socket 4 cores per socket server a "beast". (Still running too but with some kock off 8 core qualifying samples i got off ebay for mucho cheap price, warranty lasts till you open the box type of deal, but they will hold out till i get budget for a 24core rome.)

That is my system. Three years ago when I built it it was a nice system, especially for the price. Gonna be nice in about four or five years when these start showing up for dirt cheap on eBay lots when AMD's moved on to 128 core 1GB cache mid-tier processors.