"Just" a 32 Core
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AMD Announces EPYC 7532 + EPYC 7662 As Newest Rome Processors
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Originally posted by pegasus View PostSo they're still holding back on the lower core count cpus with full cache? Or maybe the niche for those cpus is just too small for them ... It's maybe easier to develop a bios feature to disable some number of cores per ccx.
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Originally posted by andrewjoy View Post
What a time to be a sysadmin. When single socket 32 core processors are the mid tier ...... . Not long ago i remember a sysadmin calling a dual socket 4 cores per socket server a "beast". (Still running too but with some kock off 8 core qualifying samples i got off ebay for mucho cheap price, warranty lasts till you open the box type of deal, but they will hold out till i get budget for a 24core rome.)
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Originally posted by starshipeleven View PostCache is a pretty big surface area (relatively speaking) so yeah, defect caches are a thing just as defect cores.
My underlying question is if you can disable low performing /defective areas as easy as you can disable "core" unit or is it necessary to take the cache as a whole. For the sake of simplicity let us just talk about L3.
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Originally posted by CochainComplex View Post(thats why modern chips have issues with radiation hardness for space equipment - very nice dense grid which can easily affected by some charged particle passing by...sry OT).
Older chips are actually very much larger in surface space (at the same relative performance), they are printed at 80nm or even bigger process nodes.
I mean, how many Pentium IV do you need to amass to actually get anywhere near the performance of a modern CPU? how much square meters of silicon surface is that lol?
My underlying question is if you can disable low performing /defective areas as easy as you can disable "core" unit or is it necessary to take the cache as a whole. For the sake of simplicity let us just talk about L3.
Otherwise having a single defect in the cache block would mean you have to disable the whole block so you end with some cores that have no attached L1/L2/L3 cache, that's insane, you are trashing that core's performance.
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Originally posted by pegasus View PostSo they're still holding back on the lower core count cpus with full cache? Or maybe the niche for those cpus is just too small for them ... It's maybe easier to develop a bios feature to disable some number of cores per ccx.
so I’m wondering why do you want fewer cores, it makes no sense to me.
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