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Linux Kernel Preparations For RISC-V Vector ISA Support

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  • Linux Kernel Preparations For RISC-V Vector ISA Support

    Phoronix: Linux Kernel Preparations For RISC-V Vector ISA Support

    While still a draft standard, support for the RISC-V "V" Vector Extension support for the Linux kernel is currently being prepared...

    http://www.phoronix.com/scan.php?pag...tor-Linux-Prep

  • #2
    Michael you need to fix your via link <a href="https://github.com/riscv/riscv-v-spec'>this GitHub repository</a> Single quote at the end of the href

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    • #3
      Seems you might have left out the end of the article there, Michael.
      "RISC-V Vector Extension can find the current draft specification via" ... and the article ends there.

      Edit: Thanks for fixing!
      Last edited by nottin; 01-06-2020, 07:58 AM.

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      • #4
        What are the vector extensions good for?
        What are they used for?
        Is this for graphics? cryptography?

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        • #5
          Originally posted by uid313 View Post
          What are the vector extensions good for?
          What are they used for?
          Is this for graphics? cryptography?
          They're for any applications that manipulate a large amount of data in the same manner, not just limited to graphics or cryptography, for example operating on a vector, array, matrix...
          Just another SIMD solution corresponding to SSE, AVX, Neon, AltiVec... in other architectures

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          • #6
            Originally posted by uid313 View Post
            What are the vector extensions good for?
            What are they used for?
            Is this for graphics? cryptography?
            The vector extension are the equivalent of these intruction sets:
            - X86/AMD64: MMX, SSE, SSE2, SSE3, SSE4, AVX, AVX2, etc...
            - ARM: Neon
            - PowerPC: Altivec
            - Cray: since the early 1970s

            The RISCV vector instructions are designed to be much more simple, compatible and flexible, while being powerful as designer want to spend in hardware/silicon.

            In Packed/SIMD set (like SSEs, AVXs) for each bit width and vector size you have a specific instruction.

            However in RISCV the programmer can set the registers VLEN/XLEN to the desired size and the hardware will adapt independent of size/throughput.

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            • #7
              Originally posted by phuclv View Post
              They're for any applications that manipulate a large amount of data in the same manner, not just limited to graphics or cryptography, for example operating on a vector, array, matrix...
              Just another SIMD solution corresponding to SSE, AVX, Neon, AltiVec... in other architectures
              It's not exactly SIMD, it's more similar to old Cray vectors, or SVE (on ARM).
              The nice thing about it is that you can run the same code with good performance on a wide range of sizes of vector processor. One of the pain points of SIMD is that every time you want to build a wider vector unit, you need to add new instructions to support it, and you can't as effectively mix older and newer vector code. With RISC-V vectors, you can implement small (but still useful) vector units for area- or cost-constrained devices, and run mostly or entirely the same vector code that you do on massive workstation CPUs, and it will be able to take advantage of the wider units (if your code has that degree of inherent parallelism).

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              • #8
                Originally posted by uid313 View Post
                What are the vector extensions good for?
                What are they used for?
                Is this for graphics? cryptography?
                Definitely useful for graphics, and for cryptography. For example, you could implement ChaCha20 as a pipeline in this, fairly simply I think. The more crypto-oriented extensions under consideration right now are implemented as extensions to the vector extension.
                Last edited by microcode; 01-06-2020, 12:54 PM.

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                • #9
                  Can this be used for a iGPU (integrated GPU) on a RISC-V CPU?
                  Also will this be used by those RISC-V GPU projects mentioned on Phoronix?

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                  • #10
                    Originally posted by uid313 View Post
                    Can this be used for a iGPU (integrated GPU) on a RISC-V CPU?
                    Also will this be used by those RISC-V GPU projects mentioned on Phoronix?
                    Well, I think the core idea of RISC-V GPU was to add a bunch of special graphics instructions and roll with it.

                    The problem imho is that modern (I)GPUs are pretty powerful, typically use SIMT (pushing multiple threads through SIMD units), have hardware schedulers etc. A CPU with graphics extensions can not compete with that.

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