Originally posted by wizard69
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Intel Details New Data Streaming Accelerator For Future CPUs - Linux Support Started
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Originally posted by timofonic View PostSeparate or integrated into the CPU die?
If it were larger, I'd just say "in-package". However, something like this is probably much too small to put on its own die. Maybe as part of an "I/O die", if Intel follows AMD's Zen2 approach...
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Originally posted by mrugiero View PostWhat do you mean here? How are those related?
So, the value proposition of a dedicated DMA engine is much lower. Not to speak of a 28-core CPU with 56 threads, or a 64-core CPU with 128 threads.
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Originally posted by coder View PostOh, quite simply. If you only have one CPU with one hardware thread, then the idea of tying it up with data movement is very unpalatable. However, if your CPU has 8 cores with 16 hardware threads, and one of them is tied up doing data movement across PCIe to a slow device, then you almost don't notice or much care - especially since that thread might be paired with a compute-heavy thread that keeps most of the core's functional units busy, anyhow.
So, the value proposition of a dedicated DMA engine is much lower. Not to speak of a 28-core CPU with 56 threads, or a 64-core CPU with 128 threads.
Further, big.LITTLE in the ARM world can be seen that way, maybe even more than HT.
There are use cases, though. For example, deep packet processing at line rate on high speed interfaces requires saturating all cores, and not everyone has many cores either, specially in the in-development world.
For example, I live in Argentina, and 2-4 threads are still common, even in retail computers, and that's also still very common in cellphones AFAIK.
But yeah, I see your point.
I have no idea if ARM does DMA tho.
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Originally posted by mrugiero View PostThere are use cases, though.
Originally posted by mrugiero View PostFor example, deep packet processing at line rate on high speed interfaces requires saturating all cores, and not everyone has many cores either,
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Originally posted by mrugiero View PostI have no idea if ARM does DMA tho.
DMA is also very much there in any SoC as all processors in the SoC (CPU, GPU, modems, hardware decoding for media, and more) are sharing the same RAM.
One of the reasons projects like Purism's phone have the modem on USB bus (electrical USB interface) instead than integrated in the SoC is just that. The modem will have its own RAM and its own stuff and will have no access to the "app processor" (the main CPU running the OS) world.
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Originally posted by jayN View PostSapphire Rapids does have a DSA, according to recent slide leaks.
There is also an Oct 2020 detailed spec available at this link
https://software.intel.com/content/w...ification.html
I have to wonder how much of that can just be handled by a few CPU threads. With CPUs having SMT and so many cores, we don't need things like DMA engines, any more. Sure, it's a little bit of a waste to burn a big CPU core on that stuff, but a win for programmability.
If I had to chose between an Intel CPU with those engines but fewer cores, or an AMD/ARM CPU with more cores for the same or less $$$, my choice wouldn't be the Intel CPU.
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Originally posted by coder View PostWith CPUs having SMT and so many cores, we don't need things like DMA engines, any more.
Intel added CXL on Sapphire Rapids also. It has biased cache coherency, but there may need to be some dma transfers between processor cache and accelerator memory when the bias is flipped. I wonder if they plan to use the DSA to do those transfers.
The operations of creating and applying Delta records is interesting, too. Perhaps it can be used to minimize writes to NVM.
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