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Intel Details New Data Streaming Accelerator For Future CPUs - Linux Support Started

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  • Intel Details New Data Streaming Accelerator For Future CPUs - Linux Support Started

    Phoronix: Intel Details New Data Streaming Accelerator For Future CPUs - Linux Support Started

    The "Data Streaming Accelerator" (DSA) is a new block on future Intel CPUs that hasn't been talked about much publicly... Until now. Intel's open-source crew has begun detailing DSA for future Intel CPUs that will offer high-performance data movement and transformation operations. The Linux driver enablement has begun...

    http://www.phoronix.com/scan.php?pag...treaming-Accel

  • #2
    Intel is such a baller when it comes to driver support. Can't wait for their dGPU!

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    • #3
      Considering that Intel messed up memory security, and switching between user and kernel space got more expensive due to that, this seems like a bad attempt to mitigate the performance loss. I'm worried that the complexity of this feature will cause just more security nightmares.

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      • #4
        Originally posted by DoMiNeLa10 View Post
        Considering that Intel messed up memory security, and switching between user and kernel space got more expensive due to that, this seems like a bad attempt to mitigate the performance loss. I'm worried that the complexity of this feature will cause just more security nightmares.
        Maybe they hurried it up because of those reasons, but this seems valuable by itself, so it was probably in store even before these issues came to light.
        I may be naive.

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        • #5
          Wow, I figured Hyper Threading killed DMA, but this sounds like DMA on steroids. One benefit might be lower-overhead/lower-latency context switching between data streams, in addition to simply being able to handle more data streams than you'd care to burn hyperthreads on.

          a Non-Transparent Bridge (NTB) device to/from remote volatile and persistent memory on another node in a cluster.
          That even sounds a bit like taking on the NVLink use case, or at least a piece of it. Of course, there still needs to be a capable PHY, but at least this might be able to handle the routing.

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          • #6
            Originally posted by DoMiNeLa10 View Post
            Considering that Intel messed up memory security, and switching between user and kernel space got more expensive due to that, this seems like a bad attempt to mitigate the performance loss. I'm worried that the complexity of this feature will cause just more security nightmares.
            Aren't they pushing some new special memory for the same reasons? I recall reading about that somewhere...

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            • #7
              Back to the past. Old DMA resurrected again.

              Do we live in circles?

              Will we see the resurrection of Amiga architecture too? Copper?

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              • #8
                Originally posted by timofonic View Post
                Back to the past. Old DMA resurrected again.

                Do we live in circles?

                Will we see the resurrection of Amiga architecture too? Copper?
                It's actually not a bad idea, if done right. Sounds a bit like mainframe-style channel I/O, which would be really amazing.

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                • #9
                  Originally posted by HyperDrive View Post
                  It's actually not a bad idea, if done right. Sounds a bit like mainframe-style channel I/O, which would be really amazing.
                  Still sounds like every chain-able DMA Hardware I ever worked with? Every SOC nowadays has these without Phoronix going bonkers about it.

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                  • #10
                    Originally posted by discordian View Post

                    Still sounds like every chain-able DMA Hardware I ever worked with? Every SOC nowadays has these without Phoronix going bonkers about it.
                    I’m not so sure, it sounds more like an intelligent I/O processor than any thing else. Hopefully more info will come soon.

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