Centaur Tech Announces Eight-Core x86 SoC With AI Coprocessor

[willmore]

VIA is still using the Centaur name for processors? Centaur was a separate company from Cyrix that VIA bought around the same time. In the late 90's they made the IDT WinChip processors which were very cheap, but horrible, horrible.

What? The C6 was a great chip. It had more cache than any of its competetors at the time and it used very little power. I ran one for over a decade as a router.

[libv]

Someone should just step up and buy this remnant of VIA to gain an x86 license. In fact, it could be that this paper launch is meant to elicit just that.

[the_scx]

If/when this SoC hits retail channels, it should be well supported on Linux considering most AI inference happening there.

They use Ubuntu 18.04 LTS.
https://centtech.com/wp-content/uplo...18_Release.pdf - page 7

https://github.com/mlperf/inference_results_v0.5/blob/b74c350644c7e47c95e98e9d1200db2d6561ebe7/closed/CentaurTechnology/systems/0.json#L24

But beyond that, as we've reported in recent kernel cycles, Centaur has been ramping up their Linux kernel support as well as for Zhaoxin CPUs that is the Chinese VIA joint venture.

I am afraid that VIA/Centaur Technology may not have access to the latest Zhaoxin microarchitectures, especially ZX-D (Wudaokou ~2017), ZX-E (Lujiazui ~2018) and ZX-F (~2019).

https://browser.geekbench.com/v5/cpu/526995

Anyway, these patches you are talking about have been provided by Zhaoxin.

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=761fdd5e3327db6c646a09bab5ad48cd42680cd2

Would be interesting to see how close in feature set they come out with.

• Centaur developed a new x86 microprocessor with high instructions/clock (IPC)
  • Microarchitecture designed for server-class applications with extensions as AVX-512
  • New x86 technology now proven in silicon with 8 CPU cores and 16MB L3 caches
  • SoC architecture provides an extensive platform with 44 PCIe lanes and 4 channels of PC3200
• Including AI coprocessor, requires less than 195mm^2 in 16nm TSMC
• Reference platform running at 2.5GHz today
  • Simultaneous execution of x86 cores and 20 TOPS AI Coprocessor
  • Delivers 20 peak terabytes/sec to AI Coprocessor from dedicated 16MB SRAM
• Centaur’s internal code name: "NCORE"
  • SoC design is "CHA", and x86 core is "CNS"

2008 - VIA CN Nano, first revision of Isaiah, e.g. Nano L2100
2009 - CNB (VIA Nano 3000 Series), e.g. Nano L3025
2011 - CNC (VIA Nano X2 - two Nano 3000 in the same die), e.g. Nano X2 L4050
2011 - CNQ (VIA Nano QuadCore - two Nano X2 in a multi-chip module), e.g. Nano QuadCore L4650E
2015 - CNR (VIA Nano QuadCore, Isaiah II), e.g. Nano QuadCore C4650
2019 - CNS (new CPU with AI coprocessor)

To be honest, the first samples of Isaiah II were produced in 2014. Zhaoxin used it to develop their own µarch.

MLPerf Inference v0.5 Results

COCO object detection on SSD MobileNet v1 (images/sec)
- Intel Core i3-1005G1 1.2GHz to 3.4GHz Ice Lake 2C/4T (Intel® UHD Graphics): 217.93 (33.43%)
- Centaur Integrated x86 CPUs @ 2.5GHz ~ 2.3GHz 8C/8T (Centaur Integrated AI Coprocessor): 651.89 (299.13%)

ImageNet image classification on MobileNet v1 (images/sec)
- Intel Core i3-1005G1 1.2GHz to 3.4GHz Ice Lake 2C/4T (Intel® UHD Graphics): 507.71 (8.40%)
- Centaur Integrated x86 CPUs @ 2.5GHz ~ 2.3GHz 8C/8T (Centaur Integrated AI Coprocessor): 6042.34 (1190.12%)

ImageNet image classification on ResNet-50 v1.5, (images/sec)
- Intel Core i3-1005G1 1.2GHz to 3.4GHz Ice Lake 2C/4T (Intel® UHD Graphics): 100.93 (8.28%)
- Centaur Integrated x86 CPUs @ 2.5GHz ~ 2.3GHz 8C/8T (Centaur Integrated AI Coprocessor): 1218.48 (1207.25%)

Source: https://www.forum-3dcenter.org/vbull...3#post12145953

Probably no HT and no VT-x.

It has 8 cores. Why should it support SMT if we already know that it is a big source of hardware bugs?

SMT (Simultanious Multi Threading) implementations typically share TLBs and L1 caches between threads. This can make cache timing attacks a lot easier and we strongly suspect that this will make several spectre-class bugs exploitable. Especially on Intel's SMT implementation which is better known as Hypter-threading. We really should not run different security domains on different processor threads of the same core. Unfortunately changing our scheduler to take this into account is far from trivial. Since many modern machines no longer provide the ability to disable Hyper-threading in the BIOS setup, provide a way to disable the use of additional processor threads in our scheduler. And since we suspect there are serious risks, we disable them by default. This can be controlled through a new hw.smt sysctl. For now this only works on Intel CPUs when running OpenBSD/amd64. But we're planning to extend this feature to CPUs from other vendors and other hardware architectures.

Note that SMT doesn't necessarily have a posive effect on performance; it highly depends on the workload. In all likelyhood it will actually slow down most workloads if you have a CPU with more than two cores.

Source: https://www.mail-archive.com/source-.../msg99141.html

As for virtualization, VIA Nano supports VIA VT (compatible with Intel VT-x) for a very long time, at least since CNB (2009) AKA single core VIA Nano 3000 Series CPUs, e.g. Nano L3025 or Nano U3100.

[archsway]

Not just that, but a CPU that isn't obsolete before it's released. Sure, it isn't impressive but those specs certainly aren't bad.

Are you assuming its release date?

[Chugworth]

What? The C6 was a great chip. It had more cache than any of its competetors at the time and it used very little power. I ran one for over a decade as a router.

I had one back in the late 90's. It caused frequent blue screens on Win9x. NT4 ran better, though it was not really ideal for home use. As I recall, there was a switch in the BIOS for the L2 cache, and the system actually ran more stable when it was off.

Thinking back to it, those were the days when all processor brands used Socket 7, so maybe there was just some compatibility issue between it and the motherboard that I was using. I certainly don't remember for sure, but it very likely would have had a VIA chipset.

[willmore]

I had one back in the late 90's. It caused frequent blue screens on Win9x. NT4 ran better, though it was not really ideal for home use. As I recall, there was a switch in the BIOS for the L2 cache, and the system actually ran more stable when it was off.

Thinking back to it, those were the days when all processor brands used Socket 7, so maybe there was just some compatibility issue between it and the motherboard that I was using. I certainly don't remember for sure, but it very likely would have had a VIA chipset.

Ouch. I didn't run Windows on it, so I never ran into those problems. Ran Linux just fine. I only replaced it when I went to >100Mb/s internet and the DEC Tulip fast ethernet boards in it ran out of steam.

[coder]

Someone should just step up and buy this remnant of VIA to gain an x86 license. In fact, it could be that this paper launch is meant to elicit just that.

I'd imagine they're too tightly wrapped up in joint ventures with Via's Chinese partner (some state-backed investment, IIRC).

[coder]

Wonder where they got that IP.

Really? Everyone is making AI engines. At a fundamental level, they're really very simple.

Regarding IP, the key question would be whether there's anything clever or unique about their implementation. A few have things like hardware compression of weights, special numerical formats, etc.

[coder]

Holy smokes... Via/Centaur is still alive and making new CPUs.

I had honestly written them off at this point.

I guess you missed Phoronix' coverage of Zhaoxin, then?

https://www.phoronix.com/scan.php?page=news_item&px=Zhaoxin-Linux-5.3-Improvements

[schmidtbag]

Are you assuming its release date?

Most of the time, CPUs are released within 1 year of their announcement. So yes, I'm assuming this will be released before 2021.
I think all of us here can agree that deca-core x86 CPUs are not going to be obsolete in that amount of time.