Zombieload V2 TAA Performance Impact Benchmarks On Cascade Lake

[Guest]

It will be interesting to test the cumulative effect of all the mitigations intel's cpus were subject to the last couple of years. All on vs all off.

And make sure older chips are tested as well, at least back to core 2 duo days, as these CPUs are still borderline usable, and I'd love to see impact depending on the microarchitecture and present bugs.

[marlock]

In most benchmarks, disabling TSX has similar or greater performance than enabling it (even without mitigations!)... so I'm left wondering... Is there any use for TSX beyond improving performance?

I ask because if there isn't, the most reasonable course of action seems to be just killing TSX for everyone by default (and maybe, just maybe, left for optional enabling with mitigations in the rare loads it actually helps while mitigated... if it isn't a big developer time-drain).

And can Intel have a word with the R&D people from back then and ask them Wisky Tango Foxtrot was that all about?!

I can hardly wait for the next round of Intel vs AMD retrospective cumulative mitigation benchmarks...

And finally, lets consider a metaphor between the last dozen Intel cpu oopses (all obviously totally not on purpose) and a bar that frequently makes mistakes when closing client tabs and giving change (always to its own benefit, but also obviously totally not on purpose)...

[geearf]

It seems there is something wrong with the fix. When TSX on and vulnerable or off have about the same efficiency, I'd assume TSX to not be needed and yet with the fix it's most often quite worse when I'd expect no impact. Do apps need to be properly rebuilt too?

[xpue]

...

vendor_id    : AuthenticAMD
bugs        : tlb_mmatch fxsave_leak sysret_ss_attrs null_seg spectre_v1 spectre_v2

[ldesnogu]

It will be interesting to test the cumulative effect of all the mitigations intel's cpus were subject to the last couple of years. All on vs all off.

I definitely would like to see that comparison too. I'd also like to see the impact of microcode changes, but I guess that's much more complex as you'd need to find chips with old microcode.

[msroadkill612]

I guess they'll end up on Bulldozer performance or something. The same level that all sorts of people blamed AMD for having. Seems intel only won the past race due to driving without helmet, seat belt, safety goggles or brakes. ;-)
Ah, well. Back to enjoying my relatively error free AMDs and elderly in-order-chips.

Don't anyone get me wrong: mistakes happen. But what intel delivers here is close to being on purpose and same level as certain car manufacturers with their exhaust gas cheatery.

Wow. That is very quotable sagacity. I hope you don't mind if I do . Kudos dude.

[Spacefish]

This CPU was launched in Q2/19

processor : 7
vendor_id : GenuineIntel
cpu family : 6
model : 85
model name : Intel(R) Xeon(R) Gold 6240 CPU @ 2.60GHz
stepping : 7
microcode : 0x5000029
cpu MHz : 2593.906
cache size : 25344 KB
physical id : 14
siblings : 1
core id : 0
cpu cores : 1
apicid : 14
initial apicid : 14
fpu : yes
fpu_exception : yes
cpuid level : 22
wp : yes
flags : a lot
bugs : cpu_meltdown spectre_v1 spectre_v2 spec_store_bypass l1tf mds swapgs taa itlb_multihit
bogomips : 5187.81
clflush size : 64
cache_alignment : 64
address sizes : 43 bits physical, 48 bits virtual
power management:

[starshipeleven]

This CPU was launched in Q2/19

processor : 7
vendor_id : GenuineIntel
cpu family : 6
model : 85
model name : Intel(R) Xeon(R) Gold 6240 CPU @ 2.60GHz
stepping : 7
microcode : 0x5000029
cpu MHz : 2593.906
cache size : 25344 KB
physical id : 14
siblings : 1
core id : 0
cpu cores : 1
apicid : 14
initial apicid : 14
fpu : yes
fpu_exception : yes
cpuid level : 22
wp : yes
flags : a lot
bugs : cpu_meltdown spectre_v1 spectre_v2 spec_store_bypass l1tf mds swapgs taa itlb_multihit
bogomips : 5187.81
clflush size : 64
cache_alignment : 64
address sizes : 43 bits physical, 48 bits virtual
power management:

And someone still thinks Intel makes a "whole new microarchitecture" every four years.

[pelweini]

So there is only one benchmark where TSX with mitigations is now faster than disabling TSX. That is SVT-VP9 0.1, and it is margin-of-error kind of difference (252 vs 250 FPS). As far as I know, the reason for this feature to exist was to improve performance. Now it seems to do the opposite.

These Intel speculative execution bugs are a gift that just keeps on giving! Not even to mention that the Intel's first implementation of TSX was buggy beyond being fixable by microcode, and it was simply disabled via a microcode update.

Thank you.