Announcement

Collapse
No announcement yet.

Benchmarks Of JCC Erratum: A New Intel CPU Bug With Performance Implications On Skylake Through Cascade Lake

Collapse
X
 
  • Filter
  • Time
  • Show
Clear All
new posts

  • Benchmarks Of JCC Erratum: A New Intel CPU Bug With Performance Implications On Skylake Through Cascade Lake

    Phoronix: Benchmarks Of JCC Erratum: A New Intel CPU Bug With Performance Implications On Skylake Through Cascade Lake

    Intel is today making public the Jump Conditional Code (JCC) erratum. This is a bug involving the CPU's Decoded ICache where on Skylake and derived CPUs where unpredictable behavior could happen when jump instructions cross cache lines. Unfortunately addressing this error in software comes with a performance penalty but ultimately Intel engineers are working to offset that through a toolchain update. Here are the exclusive benchmarks out today of the JCC erratum performance impact as well as when trying to recover that performance through the updated GNU Assembler.

    Phoronix, Linux Hardware Reviews, Linux hardware benchmarks, Linux server benchmarks, Linux benchmarking, Desktop Linux, Linux performance, Open Source graphics, Linux How To, Ubuntu benchmarks, Ubuntu hardware, Phoronix Test Suite

  • #2

    Comment


    • #3

      Comment


      • #4
        Fffffffffff-

        Comment


        • #5
          I am mystified by how a bug in conditional branch instructions could have been overlooked for 5 years in what has to be the most widely-deployed CPU design in the world. Surely that's among the most common classes of instructions in any program? I can't imagine how fixing something that seems to be astronomically improbable would be worth the performance hit, vs just patching the affected applications.

          Comment


          • #6
            Originally posted by Nille View Post
            It's not over yet, another variant of Zombieload affecting event the latest cores is out as well

            Comment


            • #7
              Originally posted by blargh4 View Post
              I am mystified by how a bug in conditional branch instructions could have been overlooked for 5 years in what has to be the most widely-deployed CPU design in the world. Surely that's among the most common classes of instructions in any program? I can't imagine how fixing something that seems to be astronomically improbable would be worth the performance hit, vs just patching the affected applications.
              Well, that is Intel for you skipping steps to bathe in that sweet moneyz

              The problem with silicon bugs is that basically is extremely hard to be sure what qualifies as "Affected" and they have to assume if they are any good at their jobs that anything can triggers it because the silicon is flawed and outside Fuzzying every possible iteration of every possible iteration you don't know in practice if any of those combination could actually trigger the bug. This is why they are called "Mitigations" and not "Fixes".

              On the bright side this defect is only present in the last few generations, mostly all others go back all the way.

              Comment


              • #8
                Originally posted by numacross View Post

                It's not over yet, another variant of Zombieload affecting event the latest cores is out as well
                Yaaaayyyy

                Comment


                • #9
                  Originally posted by blargh4 View Post
                  I can't imagine how fixing something that seems to be astronomically improbable would be worth the performance hit, vs just patching the affected applications.
                  Wouldn't that still allow VMs to escape their sandbox and leak host kernel memory or other (very) sensitive information?

                  Comment


                  • #10
                    So will the updated assembler affect AMD performance....?

                    Comment

                    Working...
                    X