SiFive U8-Series To Offer Much Greater RISC-V Performance

[tg--]

Can any company make and sell an ARM CPU without paying hefty royalties to ARM?

No they cannot. Using the ARM ISA requires companies to get a license from ARM.
Though that very likely will change in the near future (due to RISC-V mainly).

Can any company besides Intel and AMD even make X86 CPUs?

Yes, Intel and AMD can both license out X86.
There's 2 other X86 CPU companies right now: Zhaoxin, which uses the old VIA x86 license, and THATIC, which is joint-venture between AMD and a consortium of Chinese companies under the direction of the Communist Party.

This is highly interesting:
how is RISC-V architecture flawed compared to others when all that RISC-V is is an instruction set?

It cannot. However, the architectures based on the RISC-V ISA could be flawed (like SiFives), and very likely are - because all architectures are flawed in some sense.

[hajj_3]

Sorry, but what is so interesting about it? It's a Cortex-A72 class design performance-wise - neat, but nothing astonishing (and no SIMD, yet).

It is better than A-72, 50% more performance and 2x better density. It will likely offer performance similar to A-73. A-73 is still shipping in lots of mid-range android phones.

[tuxd3v]

It is better than A-72, 50% more performance and 2x better density. It will likely offer performance similar to A-73. A-73 is still shipping in lots of mid-range android phones.

It his not 50% more performance than A72..
What they say its that it Should offer competitive performance Against A72..

So in performance its in the same magnitude scale, but they achieve that at 2.6Ghz( while majority of a72 are in the 1.8-2.0Ghz tough they are thinking in a 7nm node size..wereas A72 is 28nm I believe, here they have an advantage since they can scale up Frequency, for less power.. ).

[cipri]

Meh... I'm not interested in RISC-V any longer ¯\_(ツ)_/¯

It seems to be just a bunch of buzzwords put together. In the end: there is no real world CPU, there is no more freedom and there is no software support.

Also I've heard that the architecture is very flawed compared to others

depends from who you heard!
Maybe you heard NVIDIA?

https://syncedreview.com/2019/10/10/is-nvidia-doubling-down-on-risc-v/

Or Alibaba?
https://www.theregister.co.uk/2019/07/27/alibaba_risc_v_chip/

Or Maybe Western Digital?

https://www.anandtech.com/show/13964/western-digitals-riscv-swerv-core-released-for-free

You might not know, but you can check linux running on risc-v (check youtube).
The last released version of llvm supports risc-v out of the box......

Why do you think, such huge names are behind risc-v??
Alone SiFive has more than 500 employees, and they just started!

[cipri]

In my dreams they would collaborate with the Raspberry foundation to make a Raspberry Pi Model C, mass producted so it's less then hundret bucks (but Model B prices are just too unrealistic).

Yes some people have strange dreams.
there are already completely open source risv cpus. Do you think rpi devs are interested??? No, they are broadcom employees, they want to sell the broadcom chips!
This will happen when broadcom will start to produce and sell risc-v chips! And very likely, this will happen in the next years.

[ldesnogu]

The reason I get excited about RISC-V is that all other instruction sets were designed in the era when numbers of transistors per chip was counted in thousands and the intent of instruction sets was to improve performance relative to that era technology (X86 was in the 'microcoded' era, ARM was in 'single issue pipeline and no cache' era).

ARM 64-bit ISA was designed in the 2010s. It's not the old ARM 32-bit anymore.

In the meanwhile technology had advanced, we re counting transistors in millions and billions, there's superscalar pipelines, out-of-order speculative execution, register renaming and other stuff in modern CPUs. For 90% of the ISA this doesn't matter a lot, but in edge cases, there's a lot of extra cruft in the implementation of a CPU there simply due to needing emulate quirks of archaic ISAs. And these are often things that are hindering the whole architecture of the CPU (think of ARM32 conditional instructions - maybe a good idea for 1985 to save a few transistors, but definitely a great pain for implementations in 2019; yes they have dropped them in ARM64 ISA, but all modern CPUs still implement them for backward compatibility reasons).

RISC-V was designed to match state of the art HW of 2010s rather than 1970-1980ies. This is why they don't need extra pipeline stages for decoding X86 instructions into internal core uOPs (and consequenially they have shorter pipeline stalls at branch mispredictions). They don't need uOP caches. Instruction fusing is simpler etc.

RISC-V ISA shortcomings will require some work at the micro-arch level to overcome them to extract performance. As an example the lack of reg + reg addressing mode.

RISC-V processors have been shown to match performance levels of other ISA CPUs with RISC-V having considerably less transistors (and consuming less power). A lot of that is due to not having to deal with backward compatibility (X86-32, ARM-32 are both extremely complex and most 64-bit CPUs still implement them), but a large part is simply that a modern ISA is easier to implement efficiently.

Care to share link?

[blargh4]

It is better than A-72, 50% more performance and 2x better density. It will likely offer performance similar to A-73. A-73 is still shipping in lots of mid-range android phones.

Maybe at 7nm, but according to the announcement, they have "comparable" SPECint performance when both fabbed in 16nm. Jury's out on floating point performance but I'm guessing they'd include it if the comparison was favorable. And the area comparisons seem not quite apples-to-apples, since the A72 has NEON and will eat this thing for lunch on vectorizable code.

Don't get me wrong, it's nice that the RISC-V world has a solid "big" core design, it's just not game-changing outside the RISC-V ecosystem. I'd be more interested once I can get my hands on some hardware I can hack on without spending an outlandish amount of money.

[pkese]

Care to share link?

https://riscv.org/wp-content/uploads/2015/01/riscv-rocket-chip-generator-workshop-jan2015.pdf

slide 7

[Almindor]

This is more about SiFive the company and their approach to support than about this board. I have the hifive1-revB board and have been playing around with it and Rust for some time.

SiFive is highly dissapointing when it comes to proper documentation and access. They still didn't open up docs for the on-board Wifi and BT chips, nor have they properly explained why the OTP code that comes with the RevB contains a backup register writing piece of reset code (due to "licensing"). There's also some oddity in their "bootloader" which is actually completely useless but nevertheless does some changes to state that cause inconsistencies across resets when using the PMU.

All these issue have been asked about on their forums and while SOME explanations were given the sources remain closed and their logic very suspect. This is NOT an open source friendly company.

[blargh4]

https://riscv.org/wp-content/uploads...op-jan2015.pdf
slide 7

The relative impact on hardware complexity is going to be very different between a simple scalar pipeline like the A5 (a glorified microcontroller) and a big, wide out-of-order design. With a big OoO engine and all the supporting infrastructure you need to keep it fed, decoding is going to be a much smaller contribution to overall complexity.

That kind of simple pipeline is essentially what the RISC-V ISA and its ancestors were optimized for. It's all instructions that can be tightly pipelined in a simple manner - at the cost of overall instruction count and binary size. For high performance uarches that inherently require a lot of complexity, whether ISA minimalism is advantageous at all is far less clear. RISC-V doesn't really do much that earlier minimalist RISC ISAs like MIPS weren't doing in the 90s; that battle has already been fought, and x86 won, because the ISA just isn't that important for high-performance microarchitectures, and here it's not at all obvious that minimalist RISC designs are superior to ISAs where more compact, expressive instructions (that put less pressure on instruction cache/fetch) can be split into uops optimized for the particular characteristics of the microarchitecture.