Originally posted by torsionbar28
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The Linux Kernel Is Preparing To Enable 5-Level Paging By Default
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Originally posted by torsionbar28 View PostI probably don't understand how OS paging works here, but why do we need to increase from 256 TiB limit, when today, Xeon can only do 768 GiB and EPYC can do 2 TiB per socket? How are we in jeopardy of hitting this 256 TiB limit today or in the near future?
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Originally posted by wizard69 View PostOn the surface this sounds like absolute insanity. We are talking about 64 bit processors here, why would you need more than two levels of paging. Maybe I’m missing something (totally possible) but with the two address ranges, virtual and hardware it would seem like the goal should have been to reduce the number of paving levels.
This is makes me wonder how this impacts ARM and Power. Makes me wonder if there is a good web site that goes into comparing addressing in the physical and virtual worlds for these processors.Originally posted by johannesburgel View PostYou REALLY should google what paging is for.Originally posted by pkunk View PostIssue that 64 bit space is so huge that if you try to map it directly our with only few levels page table itself will eat up all your memory and much more.
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Originally posted by torsionbar28 View PostHow are we in jeopardy of hitting this 256 TiB limit today or in the near future?
Original x86-64 was limited by 4-level paing to 256 TiB of virtual address space and 64 TiB of physical address space. We are already bumping into this limit: some vendors offers servers with 64 TiB of memory today.
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Originally posted by Setif View PostData is getting bigger and bigger. Some servers have Terabytes of RAM.
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Originally posted by AsuMagic View Post[insert xkcd joke]
Originally posted by wizard69 View PostOn the surface this sounds like absolute insanity. We are talking about 64 bit processors here, why would you need more than two levels of paging.Last edited by Space Heater; 14 September 2019, 02:56 PM.
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Originally posted by wizard69 View PostWe are talking about 64 bit processors here, why would you need more than two levels of paging. Maybe I’m missing something (totally possible) but with the two address ranges, virtual and hardware it would seem like the goal should have been to reduce the number of paving levels.
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Originally posted by wizard69 View PostWe are talking about 64 bit processors here, why would you need more than two levels of paging. Maybe I’m missing something (totally possible) but with the two address ranges, virtual and hardware it would seem like the goal should have been to reduce the number of paving levels.
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