Originally posted by torsionbar28
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The Linux Kernel Is Preparing To Enable 5-Level Paging By Default
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Originally posted by andyprough View PostOnly 4 PiB? Apparently I'm going to have to downgrade my laptop. Not sure how I will run Chrome with 8 trillion open tabs all streaming Netflix now. Never going to get through all the episodes of It's Always Sunny in Philadelphia at this rate.
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I guess intel is aligning industry the wrong way yet again. Paging for paging for paging for paging.
IMOSNSHO, instead of making more nested page levels of fixed size pages, 4K-aligned extents should just be introduced to the page management 'API', along with 'interrupts' to make OS kernel (re)designate a block of physical RAM for CPU paging operations. Per paging namespace (CPL or VM nesting).
Then CPUs would be able to arrange MM internally any way they want (direct extent based MMU operations and xlate caching, or 3 levels of fixed pages, 100 levels, 100500 levels, whatever). This will give enough flexibility and compatibility, while simplifying software based memory managing logic at the same time. Huge sized pages transparency issue goes here as well.Last edited by Alex/AT; 15 September 2019, 05:12 AM.
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Intel's 5-level paging works by extending the size of virtual addresses to 57 bits from 48 bits.
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Only 4 PiB? Apparently I'm going to have to downgrade my laptop. Not sure how I will run Chrome with 8 trillion open tabs all streaming Netflix now. Never going to get through all the episodes of It's Always Sunny in Philadelphia at this rate.
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Originally posted by chithanh View PostActually, the comment on Power was on the mark. PowerPC uses hash-table paging so does not need to introduce a new translation layer just because that much memory could exist in a system.
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Originally posted by Space Heater View PostFrom the documentation on 5-level paging:
Original x86-64 was limited by 4-level paing to 256 TiB of virtual address space and 64 TiB of physical address space. We are already bumping into this limit: some vendors offers servers with 64 TiB of memory today.Last edited by torsionbar28; 14 September 2019, 09:03 PM.
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Originally posted by abott View PostServers can use non-RAM storage as RAM cache. That alone is a reason to increase it to as large as is possible at any given time.
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Originally posted by torsionbar28 View Posttoday, Xeon can only do 768 GiB and EPYC can do 2 TiB per socket? How are we in jeopardy of hitting this 256 TiB limit today or in the near future?
https://ark.intel.com/content/www/us...-2-70-ghz.html
Edit: Oops, I see someone beat me to the punch. Well, Setif 's post doesn't mention multi-socket, so I'll leave this here.Last edited by coder; 14 September 2019, 05:27 PM.
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