The Linux Kernel Is Preparing To Enable 5-Level Paging By Default

[aaronw]

While addressable DRAM is nowhere close to the 256TiB limit, this becomes important for memory mapping large data sets. Paging is also used for memory-mapped files, for example. There doesn't have to be physical memory to back every page entry.

[caligula]

How? Using some kind of sub-atomic memory technology?

Not necessarily. Just more modules. Currently I think 2-3 generations of process shrinking are technically feasible. Each process shrink may double the capacity. On top of that you have 3d stacking and high end laptops could use 10 instead of 2 memory channels in the future. It's also possible that they'll come up with something other than DRAM, some QLC NAND / DRAM hybrid perhaps.

[ThoreauHD]

IMO, it's all about supporting Optane DIMMs. Nonvolatile storage is the only way I see them getting to petabytes.

I hope not, because if that's what it's about, then they're well and truly fucked. This is a race to the cpu core, not some failed SSD crap dangling off side.

We are at the end of the Ghz race. 5 Ghz is the cap, and it only gets worse from here with die shrinks. The new Ghz is stacking everything as close as possible, as small as possible, with the least amount of heat as possible to the cpu core.

[coder]

Probably will take a similar amount of time (20 years) to reach 32 TB of RAM on every laptop. It's easy to imagine even small workstation and servers will have 10-100 times more capacity.

How? Using some kind of sub-atomic memory technology?

[Paul Frederick]

Intel really wants me to configure custom kernels, don't they? Because I certainly don't need 5 level paging support. I got a measly 8GB of RAM over here. Which is 4 times more than I ever use.

[Weasel]

It's only a matter of time. My first laptop had 16 MB of RAM (in 1997). Now my latest laptop has had 32 GB for almost a year now. Probably will take a similar amount of time (20 years) to reach 32 TB of RAM on every laptop. It's easy to imagine even small workstation and servers will have 10-100 times more capacity.

There's a thing called physical limits.

[Weasel]

On the surface this sounds like absolute insanity. We are talking about 64 bit processors here, why would you need more than two levels of paging. Maybe I’m missing something (totally possible) but with the two address ranges, virtual and hardware it would seem like the goal should have been to reduce the number of paving levels.

Your technical incompetence is astounding given how much bullshit you always spew about 64-bit and "removing cruft" in general.

[NatTuck]

wait, how does that work, why so uneven amount of bytes?

The Initial AMD64 spec is 4 level paging with 48-bit effective virtual addresses.

• Pages are 4096 bytes = 2^12, so 12 bits of the address select a byte within a single page.
• That leaves 36 bits of address. Each level of paging indexes into a 512 entry table. 512 = 2^9, so 9 bits per level.
• 12 + 9 * 4 = 48
• Five level paging adds another set of tables, so we go to 12 + 9 * 5 = 57.

I doubt we would have gotten exactly this system from a completely clean design, but this is a very reasonable progression from the way 32-bit x86 two level paging works (12 + 2*10 = 32; pages were still 4k; each table was 1024 entries).

Six level paging will be interesting. 12 + 9 * 6 = 66, so the final level of tables will only be 1/4th full. This will waste several kilobytes of memory for every process running on the system.

[bug77]

I know this is about servers, but I'm going to leave this here anyway:
All the memory I have owned over the past 20 years or so, combined, does not come close to the current limits

I'm glad this is happening. I've heard complaints from people that 48 bits is not enough for big servers, and getting closer to a 64 bit CPU with 64 bit address space is nice. Right now, I don't need that much memory, but I'm glad Intel is trying to make it possible. I also hope this won't affect older hardware without the support, as there's plenty of it out there, and most people won't need 5 level paging for some time.

I'm interested how this affects software that takes advantage of tagged pointers. Most x86_64 code assumes the address space is at most 48 bits, so 16 bits are always available for tags. Will this break v8, or cause performance regressions?